Gabriel Loh. A Time--Stamping Algorithm for Efficient Performance Estimation of Superscalar Processors. In Joint International Conference on Measurement and Modeling of Computer Systems, pages 72--81, June 2001. Home/Search Document Details and Download
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Toward Reducing Processor Simulation Time via Dynamic.. - Cook, Oliver, E. (2002) (Correct)
....and reduced microarchitecture model over a representative class of workloads and set of memory hierarchies. Because previous work has shown that it is possible to develop an accurate mathematical model to estimate out of order IPC (instructions committed per cycle) during an in order simulation [2], we chose to first look at L1 D cache miss rate as the answer of interest. We begin a simulation with a full processor model. This model is a cycle accurate, superscalar, out of order, speculative execution processor model that also models the behavior and timing of the cache hierarchy. ....
Gabriel Loh. A Time--Stamping Algorithm for Efficient Performance Estimation of Superscalar Processors. In Joint International Conference on Measurement and Modeling of Computer Systems, pages 72--81, June 2001.
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