B. Smith. Keynote Address. Proc. of the 17th Annual Int. Symp. on Comp. Arch., May 1990. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Compiling Dataflow into Threads - Efficient Compiler-Controlled.. - Schauser (1991) (2 citations) (Correct)
....Multithreaded execution appears to be a key ingredient in general purpose parallel computing systems. Many researchers suggest that processors should support multiple instruction streams and switch very rapidly between them in response to remote memory reference latencies or synchronization[AI87, Smi90, HF88, ALKK90, ACC 90] However, the proposed architectural solutions make thread scheduling invisible to the compiler, preventing it from applying optimizations that might reduce the cost of thread switching or improve scheduling based on analysis of the program. Inherently parallel ....
B. Smith. Keynote Address. Proc. of the 17th Annual Int. Symp. on Comp. Arch., May 1990.
Fine-grain Parallelism with Minimal Hardware.. - Culler, Sah.. (1991) (125 citations) (Correct)
....into question whether tolerance to latency and inexpensive synchronization require specific hardware support or merely an appropriate compilation strategy and program representation. 1 Introduction Multithreading at the instruction level may provide the key to general purpose parallel computing[26], because it allows the processor to tolerate long, unpredictable communication latency [2, 4, 17, 24, 29] In addition, this level of multithreading is required to support certain modern parallel programming languages[28] such as Id[20] and Multilisp[18] and extensions of more conventional ....
B. Smith. Keynote address. 17th Annual Int. Symp. on Comp. Arch., June 1990.
Compiler-Controlled Multithreading for Lenient Parallel.. - Schauser, Culler, von.. (1991) (36 citations) (Correct)
....Multithreaded execution appears to be a key ingredient in general purpose parallel computing systems. Many researchers suggest that processors should support multiple instruction streams and switch very rapidly between them in response to remote memory reference latencies or synchronization[AI87, Smi90, HF88, ALKK90, ACC 90] However, the proposed architectural solutions make thread scheduling invisible to the compiler, preventing it from applying optimizations that might reduce the cost of thread switching or improve scheduling based on analysis of the program. Inherently parallel ....
B. Smith. Keynote Address. Proc. of the 17th Annual Int. Symp. on Comp. Arch., May 1990.
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