JBus architecture overview. Technical report, Sun Microsystems, Apr. 2003. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Fast Subword Permutation Instructions Using Omega and Flip.. - Yang, Lee (2000) (10 citations) (Correct)
....relatively low precision data and have high levels of data parallelism. Multimedia instructions using subword arithmetic are adopted into many modern microprocessor architectures to accelerate multimedia processing. Examples are MAX[2] and MAX 2[3] extensions to HP PA RISC architecture, MMX[7] SSE[8] and SSE 2[9] extensions to Intel IA 32 architecture, IA 64[1] 3DNow [6] for AMD x86, VIS[13] for Sun SPARC and AltiVec[10] for PowerPC. The essence of these multimedia instructions is to pack several pieces of low precision data, called subwords, into a single machine word so that they can be ....
Intel Architecture Software Developer's Manual. Technical report, Intel Corp., 1999. http://developer.intel.com/design/PentiumIII.
Predictable Instruction Caching for Media Processors - Irwin, May, Muller, Page (2002) Self-citation (Processors) (Correct)
....area of multi media where the performance of the instruction cache will effect the quality of service in applications such as MPEG video decoders. Reducing the impact on performance introduced by interference has been addressed in a number of modern microprocessors. The Intel i960 [7] and XScale [1] architectures both employ schemes where the contents of the instruction cache can be protected against replacement under the control of the program being executed. This is achieved by preventing displacement of information held in one of the sets of a set associative instruction cache and forcing ....
Intel 80200 Processors based on Intel XScale Microarchitecture: Developer's Manual. Technical report, Intel, September 2000.
Characterization of TCC on Chip-Multiprocessors - Austen Mcdonald Jaewoong (2005) (Correct)
No context found.
JBus architecture overview. Technical report, Sun Microsystems, Apr. 2003.
Enhancing and Optimizing the Render Cache - Walter, Drettakis, Greenberg (2002) (5 citations) (Correct)
No context found.
Intel pentium 4 and intel xeon processor optimization reference manual. Technical Report 248966-05, Intel Corporation, USA, 2002.
Thirteenth Eurographics Workshop on Rendering (2002) - Debevec And Gibson (2002) (Correct)
No context found.
Intel pentium 4 and intel xeon processor optimization reference manual. Technical Report 248966-05, Intel Corporation, USA, 2002.
Thirteenth Eurographics Workshop on Rendering (2002) - Debevec And Gibson (2002) (Correct)
No context found.
Intel pentium 4 and intel xeon processor optimization reference manual. Technical Report 248966-05, Intel Corporation, USA, 2002. 4
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC