| Katkoori, S., J. Roy, and R. Vemuri: 1996, `A Hierarchical Register Optimization Algorithm for Behavioral Synthesis'. Proceedings of International Conference on VLSI Design. |
....capacitance transition activity. Capacitance is reduced by minimizing the number of: functional modules registers multiplexers. The allocation scheme selects a sequence of operations (variables) for a module or register such that the transition activity is reduced. Katkoori, et.al. [16] present an algorithm for register optimization during high level synthesis. The technique employs a hierarchical optimization phase which exploits the properties of module call graph and information gathered during local carrier life cycle analysis of each module. The algorithm works in tow ....
S.Katkoori, et. al., "A Hierarchical Register Optimization Algorithm for Behav- ioral Synthesis", Proc. of 9th Intl. Conf. on VLSI Design, Jan 1996, pp.120-132.
....specifications in vhdl and generates rtl designs also in vhdl. Using parallel synthesis algorithms, dss searches through vast regions of design space [16] DSS uses enhancements of force directed list scheduling [21, 20] and a hierarchical clique partitioning algorithm for register allocation [25]. dss has been used to generate numerous designs both in the university and industry and has been thoroughly tested using systematic benchmark development, test generation and simulation [52] In addition, as a byproduct of the synthesis process, dss automatically generates control 35 flow ....
Katkoori, S., J. Roy, and R. Vemuri: 1996, `A Hierarchical Register Optimization Algorithm for Behavioral Synthesis'. Proceedings of International Conference on VLSI Design.
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