N. Binh, M. Imai, A. Shiomi, A New HW/SW Partitioning Algorithm for Synthesizing the Highest Performance Pipelined ASIPs with Multiple Identical FUs, in proceedings of EURO-DAC'96, 1996. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
ASIP Design Methodologies: Survey and Issues - Jain, Balakrishnan, Kumar (2001) (Correct)
....values which can be assigned to these parameters. The parameterized architecture model suggested by almost all the techniques includes the number of functional units of different types. Gong et al. [7] consider storage units and interconnect resources also in their architectural model. Binh et al. [2, 3] emphasize on incorporating pipelined functional units in the model. Kienhuis et al. [19] put available element types (like buffer, controller, router and functional unit) and their composition rules. Composition rules generate alternative implementations of elements. All parameters together ....
....their architectural model. This results in a large design space. They have developed a retargetable estimator which takes advantage of such an architecture model. Architectures considered by different researchers also differ in terms of the instruction level parallelism they support. For example [3] and [19] do not support instruction level parallelism, whereas [7] and [12] support VLIW architecture and [9] and [20] support VLIW as well as super scalar architecture. Most of these approaches consider only a flat memory. Only [20] addresses consideration of instruction and data cache sizes ....
[Article contains additional citation context not shown here]
Binh, N.N.; Imai, M.; Shiomi, A. : "A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs.", Proceedings of the Design Automation Conference,
PSCP: A Scalable Parallel ASIP Architecture for Reactive.. - Andreas Pyttel Alexander (1998) (4 citations) (Correct)
No context found.
N. Binh, M. Imai, A. Shiomi, A New HW/SW Partitioning Algorithm for Synthesizing the Highest Performance Pipelined ASIPs with Multiple Identical FUs, in proceedings of EURO-DAC'96, 1996.
Partitioning Framework for Less Restricted Partitioning Problems - Oh, Ha (Correct)
No context found.
N. Binh, M. Imai, and A. Shiomi, "A New HW/SW Partitioning Algorithm for Synthesizing the Highest Performance Pipelined ASIPs with Multiple Identical FUs", in EuroDAC, 1996.
Rapid Configuration Instruction Selection for an ASIP: A Case.. - University (2003) (1 citation) (Correct)
No context found.
IMAI, M., BINH, N., AND SHIOMI, A. A new hw/sw partitioning algorithm for synthesizing the highest performance pipelined asips with multiple identical fus. In EURO-VHDL'96 (1996), pp. 126--131.
ASIP Design Methodologies: Survey and Issues - Jain, Balakrishnan, Kumar (2001) (Correct)
No context found.
Binh, N.N.; Imai, M.; Shiomi, A. : "A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs.", Proceedings of the Design Automation Conference, 1996.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC