C.S. Chang, D.S. Lee and C.M. Lien, "Load balanced Birkhoff-von Neumann switches, Part II: multi-stage buffering," Computer Comm., Vol. 25, pp. 623-634, 2002.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....the input ports. For a hardware scheduling algorithm to be useful, it is important that it be simple. That why iSLIP is the choice in Tiny Tera [20] and Cisco GSR [1] although it doesn t offer the best performance compared to other schemes or provide 100 throughput under non uniform traffic [21]. It is readily implemented in hardware and can operate at high speed. It was shown that iSLIP can find a matching using 3 iterations within 8 switch cycles (45 ns) for a # switch [22] Our iDRR can be readily modified to its port based version. We call it iPDRR. Because of the fixed number of ....

C. S. Chang, D. S. Lee, and Y. S. Jou, "Load balanced birkhoff-von neumann switches, part I: one-stage buffering," Computer Communications, vol. 25, 2002.

....out of order because they can trigger un necessary retransmissions. There are two approaches to preventing mis sequencing: To prevent packets from becoming mis sequenced anywhere in the router [24] or to bound the amount of mis sequencing, and use a re sequencing buffer in the third stage [25]. None of the schemes published to date would work in our 100Tb s router. The schemes use schedulers that are hard to implement at these speeds, need jitter control buffers that require N writes to memory in one time slot [25] or require the communication of too much state information between the ....

....of mis sequencing, and use a re sequencing buffer in the third stage [25] None of the schemes published to date would work in our 100Tb s router. The schemes use schedulers that are hard to implement at these speeds, need jitter control buffers that require N writes to memory in one time slot [25], or require the communication of too much state information between the linecards [24] 5.1 Full Ordered Frames First Instead we propose a scheme geared toward our 100Tb s router. Full Ordered Frames First (FOFF) bounds the dif ference in lengths of the VOQs in the second stage, and then uses ....

C.-S. Chang, D.-S. Lee and C.-M. Lien, "Load balanced Birkhoff-von Neumann switches, Part II: muki-stage buffering," Computer Comm., Vol. 25, pp. 623-634, 2002.

....of a 100Tb s router in a single rack, without sacrificing throughput guarantees. This is approximately 40 times greater than the electronic switching capacity that could be put in a single rack today. We describe our conclusion that the Load Balanced switch, first described by C S. Chang t al. in [16] (which extends Valiant s method [17] is the most promising architecture. It has provably 100 throughput. It is scalable: It has no central scheduler, and is amenable to optics. It simplifies the switch fabric, replacing a frequently scheduled and reconfigured switch with two identical switches ....

....per rack. permutations in the switching stage, vr2(t) If the inputs and outputs are not over subscribed, then the long term service opportunities exceed the number of arrivals, and hence the system achieves 100 throughput: lim 1 7 c 0, t 1 where e is a matrix full of l s. In [16] the authors prove this more rigorously, and extend it to all sequences a(t) that are stationary, stochastic and weakly mLxing. 3. A 100TB S ROUTER EXAMPLE The load balanced switch seems to be an appealing architecture for scalable routers than need performance guarantees. In what follows we ....

C.-S. Chang, D.-S. Lee and Y.-S. Jou, "Load balanced Birkhoff-von Neumann switches, Part I: one-stage buffering," Computer Comm., Vol. 25, pp. 611-622, 2002.

....by Chang et al. in [28] In their scheme, load balancing is performed by maintaining a single round robin list at the inputs (i.e. demultiplexors) for a 2stage switch. The authors show that this leads to guaranteed throughput and low average delays, although packets can be mis sequenced. In [29], the authors extend their earlier work by using the same technique proposed here: Send packets from each input to each output in a round robin manner. As we shall see, this technique helps us bound the mis sequencing in the PPS and also gives a delay guarantee for each packet. VIII. EMULATING A ....

Cheng-Shang Chang, Duan-Shin Lee and Ching-Ming Lien, "Load balanced Birkhoff-von Neumann switches, part II: multi-stage buffering " to appear in the special issue of Computer Communications on "Current Issues in Terabit Switching," 2001.

....buffer in the multiplexor stores cells where they are re sequenced and then transmitted in the correct order. 9. It will be convenient for the FIFO length to include any cells in transmission. It is interesting to compare this technique with the loadbalanced switch proposed by Chang et al. in [28]. In their scheme, load balancing is performed by maintaining a single round robin list at the inputs (i.e. demultiplexors) for a 2stage switch. The authors show that this leads to guaranteed throughput and low average delays, although packets can be mis sequenced. In [29] the authors extend ....

Cheng-Shang Chang, Duan-Shin Lee and Yi-Shean Jou, "Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering" to appear in the special issue of Computer Communications on "Current Issues in Terabit Switching," 2001.

....buffers are used at the output because of the randomized load balancing at the first stage. In one version of the PPS, fixed size coordination buffers are used at the input and output stages [17] Other examples of the SB architecture include the load balancing switch recently proposed by Chang [22] (which is a Randomized SB and achieves 100 throughput, but missequences packets) and the Deterministic SB variant by Keslassy [23] which has delay guarantees and doesn t missequence packets, but requires an additional coordination buffer) Table 2 shows a collection of results for different SB ....

....that within each class of SB routers (Deterministic and Randomized) performance can be analyzed in a similar way. For example, Randomized SB routers are usually variants of the Chang load balancing switch, and so they can be shown to have 100 throughput using the standard Loynes construction [22][24] Likewise, the Deterministic SB routers that we have examined can be analyzed using Constraint Sets (described in Section II) to find conditions under which they can emulate ideal shared memory routers. By construction, Constraint Sets also provide switch scheduling algorithms. In what ....

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C.S. Chang, D.S. Lee, Y.S. Jou, "Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering," IEEE HPSR Conference, Dallas, May 2001 [www.ee.nthu.edu.tw/ ~cschang/PartI.ps].

....The third approach attempts to pipeline the scheduler, allowing it to use out of date information [7] Although this approach does not reduce the throughput, it increases packet delay. The fourth approach, that motivated this paper, adopts a novel structure proposed by C. S. Chang et al. [16]. Their switch consists of two stages, but has no scheduler. Both stages of the switch follow a deterministic sequence of N different configurations. All that is required is that each input is connected to each output exactly once in the sequence. For example, the sequence that we will assume ....

....Bernoulli i.i.d. traffic; but no guaran tees are possible when the traffic is non uniform. In the twostage switch, the first stage effectively makes non uniform traffic uniform by spreading it evenly over the second stage. Hence the two stages might be expected to provide 100 throughput. In [16] this is proved rigorously, for a particular definition of throughput and for a broad class of arrival pro cesses. A disadvantage of the two stage switch is that cells can be mis sequenced by an arbitrary amount. Although strictly not This work was supported by a Wakerly Stanford Graduate ....

[Article contains additional citation context not shown here]

C.S. Chang, D.S. Lee and Y.S. Jou, "Load balanced Birkhoff- von Neumann switches, part I: one-stage buffering, " IEEE HPSR Conference, Dallas, May 2001

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C.S. Chang, D.S. Lee and C.M. Lien, "Load balanced Birkhoff-von Neumann switches, Part II: multi-stage buffering," Computer Comm., Vol. 25, pp. 623-634, 2002.

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C.S. Chang, D.S. Lee and Y.S. Jou, "Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering," IEEE HPSR '01, Dallas, May 2001.

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C.-S. Chang, D.-S. Lee and Y.-S. Jou, "Load balanced Birkhoffvon Neumann switches, part I: one-stage buffering," Computer Communications, Vol. 25, pp. 611-622, 2002.

....One of the key challenges to build high speed packet switches that scale with the transmission speed of fiber optics is to resolve conflicts of packets competing for the same resource. There are two common approaches. The first approach is to use electronic buffers (see e.g. 7] 14] [2], 16] As the accessing speed of electronic memory is considerably slower than the speed of fiber optics, this approach in general requires a lot of parallel buffers to achieve the needed speedup for fiber optics. The other approach is to resolve conflicts directly by optical Switches and fiber ....

C.S. Chang, D.S. Lee and C.M. Lien, "Load Balanced Birkhoff-von Neumann Switches, Part II: Multi-stage Buffering," to appear in the special issue of Computer Communications on "Current Issues in Terabit Switching," 2002.

....Engineering National Tsing Hua University Hsinchu 300, Taiwan, R.O.C. Email: cschang ee.nthu.edu.tw lds cs.nthu.edu.tw cyyue gibbs.ee.nthu.edu.tw Abstract In this paper, we propose two schemes for the load balanced Birkhoff von Neumann switches to provide guaranteed rate services. As in [7], the first scheme is based on an Earliest Deadline First (EDF) scheduling policy. In such a scheme, we assign every packet of a guaranteed rate flow a targeted departure time that is the departure time from the corresponding work conserving link with capacity equal to the guaranteed rate. By ....

..... Load balancing stage Fig. 2. The load balanced Birkhoff von Neumann switch with one stage buffering To cope with the first three drawbacks in the Birkhoffvon Neumann switch, the load balanced Birkhoff von Neumann switch with one stage buffering is proposed in [7]. The main idea is to add a load balancing stage in front of the Birkhoff von Neumann input buffered switch (see Figure 2) In a time slot, the crossbar switch at the first stage sets up connection patterns corresponding to permutation matrices that are periodically generated from a one cycle ....

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C.S Chang, D.S. Lee and Y.S. Jou, "Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering," Computer Communications, Vol. 25, pp. 611-622, 2002.

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C.-S. Chang, D.-S. Lee, and C.-M. Lien, "Load balanced Birkhoff--Von Neumann switches---Part II: Multi-stage buffering," Comput. Commun., vol. 25, pp. 623--634, 2002.

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C.-S. Chang, D.-S. Lee, and Y.-S. Jou, "Load balanced Birkhoff--Von Neumann switches---Part I: One-stage buffering," Comput. Commun., vol. 25, pp. 611--622, 2002.

No context found.

C.S. Chang, D.S. Lee and Y.S. Jou, "Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering," IEEE HPSR '01, Dallas, May 2001.

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C.-S. Chang, D.-S. Lee and Y.-S. Jou, "Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering," IEEE HPSR '01, Dallas, May 2001.

No context found.

C.-S. Chang, D.-S. Lee and C.-M. Lien, "Load balanced Birkhoff-von Neumann switches, Part II: multi-stage buffering," Computer Comm., Vol. 25, pp. 623-634, 2002.

No context found.

C.-S. Chang, D.-S. Lee and Y.-S. Jou, "Load balanced Birkhoff-von Neumann switches, Part I: one-stage buffering," Computer Comm., Vol. 25, pp. 611-622, 2002.

No context found.

C.S. Chang, D.S. Lee and Y.S. Jou, "Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering," IEEE HPSR '01, Dallas, May 2001.

No context found.

C.S. Chang, D.S. Lee and Y.S. Jou, "Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering," IEEE HPSR '01, Dallas, May 2001.

No context found.

C-S. Chang, D. Lee and Y. Jou, "Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering ," Special issue of Computer Communications on "Current Issues in Terabit Switching," 2001.

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