S. Edwards, L. Lavagno, E. A. Lee, and A. SangiovanniVincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," Proceedings of the IEEE, vol. 85, no. 3, march 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....to the system resource of the system architecture, while optimizing system performance metrics such as the execution time, hardware area (cost) and the power consumption. Some early works [13, 15, 24, 25] investigate the hardware software partitioning problem; it is di#cult to name a clear winner [11]. The system partitioning problem is a generalization of the hardware software partitioning problem . Partitioning issues for system architectures with reconfigurable logic components has also been studied [5, 16, 20] These works assume a reconfigurable device coupling with a processor core in ....

S. A. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of Embedded Systems: Formal Models Validation, and Synthesis. Proceedings of the IEEE, 85(3):366--90, March 1997.

....issue of any systematic methodology aiming at designing embedded systems is the underlying model of computation. The design process must be based on a model with precise mathematical meaning so that the different tasks from specification to implementation can be carried out systematically [Edw97]. A sound representation allows capturing unambiguously the functionality of the system, verifying its correctness with respect to certain desired properties, reasoning formally about the refinement and steps during the synthesis process, and using CAD tools in order to assist the designer ....

....that have been put into practice. However, approaches targeted especially to embedded systems are not so common. This chapter presents related work in the areas of modeling and verification of embedded systems. 3. 1 Modeling Many models have been proposed to represent embedded systems [Lav99] [Edw97], including extensions to finite state machines, data flow graphs, communicating processes, and Petri nets, among others. Some of them give a rigorous mathematical treatment to the formalism. This section presents vari 14 ous models of computation for embedded systems reported in the ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni -Vincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," in Proc. IEEE, vol. 85, pp. 366-390, March 1997.

....performance metrics such as the hardware cost, power consumption and worst case execution time. It is considered an integral part of the hardware software codesign problem. Some early investigations on the partitioning problem include [11, 13, 22, 23] it is difficult to name a clear winner [9]. More recently, partitioning issues for reconfigurable architectures have been studied [4, 14, 18] The partitioning problem is N P complete [12] It is possible to use brute force search or integer linear programming (ILP) formulations [20] for small problem instances. However, in general, the ....

S. A. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of Embedded Systems: Formal Models Validation, and Synthesis. Proceedings of the IEEE, 85(3):366--90, March 1997.

....represent two concurrent state subsystems, states are required. Some FSM variants have been developed to reduce this problem [96] 97] However, timing analysis is often difficult for these variants. Many other representations exist, each of which has its own advantages and disadvantages [98] [101]. In our system synthesis work, we have modeled embedded system behaviors and timing constraints with muti rate task sets. This is a natural model for data flow and signal processing behaviors. It is amenable to detailed timing analysis. deadline = 15 T4 T1 T5 T0 3 kb 2 kb 4 kb 4 kb period = ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli, "Design of embedded systems: Formal models, validation, and synthesis," Proc. of IEEE, pp. 366--390, Mar. 1997.

.... over inputs, outputs, and states) and produce computation results that have more restrictive ranges and states relative to nonembedded applications, the design of effective and efficient ATs for embedded systems is, in general, considerably easier than that for nonembedded systems [13] 14] [15]. Therefore, limiting the use of AT to external messages plays a dual role in performance cost reduction. Specifically, this strategy not only enables a process to perform AT less frequently, but also facilitates testing effectiveness and efficiency. This is because external messages are the ....

S. Edwards, L. Lavagno, E.A. Lee, and A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," Proc. IEEE, vol. 85, pp. 366-390, Mar. 1997.

....each module of the design, according to the language used to describe the module (C, VHDL, JAVA, SDL, ii) to manage the communication between different simulators. Formal verification tools are another possibility to validate hardware or software modules, but this approach is still immature [1]. This paper presents the implementation and evaluation of a geographically distributed co simulation tool. Currently, this co simulation tool validates heterogeneous designs at the system and RTL levels, with the software part described in C C and the hardware part described in VHDL. ....

Edwards, S., Lavagno, L., Lee, E., and Sangiovannivincentelli, A, "Design of Embedded Systems: Formal Models, Validation and Synthesis", Proceedings of the IEEE, 1997.

....all connected to a shared bus. As shown in Fig. 4, an example ASIC could be a datapath unit with registers. Alternatively, an ASIC could be a background memory. Two main, often contradictory, criteria for evaluation of system and behavioral synthesis models of computations are expressiveness [7] and suitability for optimization. While high expressiveness implies wider application domain, suitability for optimization often implies efficient implementation. For this target system, the following heterogeneous model of computation is assumed. The backbone of the model is the 8 ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli, "Design of embedded systems: Formal models, validation, and synthesis, " Proc. IEEE, vol. 85, no. 3, pp. 366--390, 1997.

....models have been proposed in the literature to represent digital systems. These models encompass a broad range of styles, characteristics, and application domains. Particularly in the field of embedded system design, a variety of models has been developed and used for system representation [13] [6]. Their features largely differ even though they all are computational models intended for heterogeneous embedded systems. Particularly, Petri nets (PNs) might be an interesting representation for this kind of systems: PNs, for instance, may fairly represent parallel as well as sequential ....

....systems; Coloured Petri nets have been also used to model embedded systems [1] On the other hand, several notions of equivalence have been addressed in various contexts for different sorts of systems. In the field of digital design there have been many proposed approaches using transformations [6]. Specifically, many of the concepts of equivalence and transformations defined for PNs attempt to overcome the state explosion problem, namely Petri nets tend to become complex even for relatively small systems. Murata [16] proposes a set of basic transformations aimed to reduce the complexity ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," in Proc. IEEE, vol. 85, pp. 366-390, March 1997.

....machine behaves in operational semantics. Other features include communication style, behavior aggregation to create more complex compositions, and how hierarchy abstracts such compositions. It should be noted that a language and a MoC are not necessarily synonymous; this will be addressed in 5. [7] 4.2 Domain Relevant MoC s While many MoC s exist, it is useful to develop a taxonomy of those MoC s relevant to our ADoI. The following come primarily from Berman [8] Edwards et al. 7] and the System Level Design Language (SLDL) Forum [1] An overview of these MoC s follows. 4.2.1 Discrete ....

....It should be noted that a language and a MoC are not necessarily synonymous; this will be addressed in 5. 7] 4.2 Domain Relevant MoC s While many MoC s exist, it is useful to develop a taxonomy of those MoC s relevant to our ADoI. The following come primarily from Berman [8] Edwards et al. [7], and the System Level Design Language (SLDL) Forum [1] An overview of these MoC s follows. 4.2.1 Discrete Event (DE) In the discrete event (DE) model, events usually carry a totally ordered time stamp indicating the time at which the event occurs. A DE simulator usually maintains a global ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni -Vincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," Proceedings of the IEEE, vol. 85, pp. 366-390, 1997.

....models, communicating processes, among others. We addressed several representative computational models used to capture hardware software systems [Cor99] The key aspects of these models are discussed and a comparison of their most relevant features is presented. Edwards et al. [Edw97] evaluate the properties of several representations employed for the design of embedded systems, based on the tagged signal model [Lee96] a framework where computational models can be compared. Similarly, Lavagno et al. Lav98] review and study some models of computation for embedded system ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," in Proc. IEEE, vol. 85, pp. 366-390, March 1997.

....systems is presented in Section 4. In Section 5 we illustrate our verification method using a real life telecom system. Finally, some conclusions are drawn in Section 6. 2. Related Work Many computational models have been proposed in the literature to represent embedded systems [Lav98] [Edw97]. Particularly, Petri nets (PNs) might be an interesting representation for this sort of systems: PNs, for instance, may fairly represent parallel as well as sequential activities, and may easily capture non deterministic constructions. In embedded systems design, Petri nets have been extended in ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," in Proc. IEEE, vol. 85, pp. 366-390, March 1997.

....to create more complex compositions, and how hierarchy abstracts such compositions. Since so many MoC s exist (indicative of the immaturity of this field) it is useful to develop a taxonomy of those MoC s relevant to the ADoI. The following come primarily from Berman [5] Edwards et al. [6], and the System Level Design Language (SLDL) Forum [1] Discrete event (DE) Finite state machine (FSM) and extensions . Synchronous reactive (S R) Dataflow (DF) including synchronous dataflow (SDF) Notational In the discrete event (DE) model, events usually carry a totally ordered ....

....performance constraints such as power consumption, etc. 17] 4. 1 ADoI based Simplifications Edwards et al. assert that many MoC s have been defined not just because of the immaturity of the field, but also due to fundamental differences, i.e. the best model is a function of the design [6]. The heterogeneous nature of most embedded systems makes multiple MoC s a necessity. In fact, in the system on a chip (SoC) application domain, many MoC s are built by combining three largely orthogonal aspects: sequential behavior, concurrency, and communication. Our aspects are slightly ....

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S. Edwards, L. Lavagno, E. A. Lee, and A. SangiovanniVincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," Proceedings of the IEEE, vol. 85, pp. 366-390, 1997.

....in an interactive manner, and the consequences of these design decisions are implemented automatically by a tool. Important steps to such an integration have been done already. Models of computation for a functional specification have been researched and good candidates have been identified [6, 14, 16]. Design transformations for various semantic models have been researched and formulated [13, 14, 16] and the formulation of specific transformations for the design of electronic systems is arguable a challenging but feasible task. Finally, we formulate our claim as hypothesis and describe an ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation and Synthesis", Proc. of the IEEE, vol. 85, no. 3, 1997.

....that can be exploited for parallel simulation. However, the potential to speed up simulation seems to be fundamentally constraint by the model of computation used. Discrete event models are inherently difficult to simulate efficiently in parallel due to the synchronizing global event queue [9]. A system model based on composite signal flow can be partitioned for parallel distributed simulation, if the following two conditions are met. A) A partition must be a causal process. However, not all the constituent processes within the partition need to be causal. B) No non periodic ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation and Synthesis", Proceedings of the IEEE, March 1997.

....used for different tasks to be performed during system analysis and design. There is a lot of research in the area of system modelling and specification, and an impressive number of representations have been proposed. An overview and classification of different design representations is given in [Edw97, Ern99]. In this thesis we use the conditional process graph [Ele98, Ele00] as an abstract model for system representation. 2.1.1 CONDITIONAL PROCESS GRAPH A process graph is an abstract representation consisting of a directed, acyclic, polar graph G(V, E S , E C ) Each node P i V represents one ....

S. Edwards, L. Lavagno , E. A. Lee , A.SangoivanniVincentelli , "Design of Embedded Systems: Formal Models, Validation and Synthesis", Proceedings of the IEEE, Vol. 85, No. 3, March 1997.

....embedded system. 1. INTRODUCTION As the complexity of embedded system grows consistently with technology improvement, hardware software codesign has been actively investigated as a new design methodology to enhance the design power accordingly in terms of design quality and design time[1][2]. Codesign methodology allows the designer to explore the design space in the early stage of design cycle by evaluating architectures without implementation. There are at least two groups of research activities targeting different style of architectures in mind. One group targets distributed ....

S. Edwards, L. Lavagno, E. A. Lee and A. SangiovanniVincentelli, "Design of Embedded Systems: Formal Model, Validation and Synthesis," Proceedings of the IEEE, vol. 85, no. 3, March 1997.

....and the remaining research on synthesis and verification are based on existing knowledge and techniques, and therefore we do not expect insurmountable problems. 2. Related Work Many computational models have been described in the literature. For a comprehensive overview see Edwards et al. [4]. Very often real time systems are specified by means of concurrent processes, which communicate asynchronously. Such a communication model forms the base for languages such as SDL [23] VHDL, or SpecCharts [14] While this model serves as a good implementation model, due to its closeness to ....

S. Edwards, L. Lavagno, E. A. Lee and A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation and Synthesis", Proceedings of the IEEE, Vol. 85, No. 3, pp. 366-390, March 1997.

....the fact that this transfer mode is fast and easy to implement, it is unacceptable for most interactions. Additional synchronization signals without data transfer can be used to improve this transfer mode. Synchronized data transfer includes methods to ensure a reliable exchange of data. In [24] FIFO buffered and rendezvous mechanisms are given as examples of synchronized data transfer. The first uses a FIFO buffer of a finite size for storing data between writing and reading. The latter demands writing and reading operations to be performed simultaneously. This is comparable to the way ....

....messages. If an already sent message proves to be incorrect an anti message is produced to cancel the message 2.4. Models of Computation In general a design consists of a set of components. A model of computation is needed to define the behaviour of the components and the interaction between them [24]. The most important models will be considered in this chapter. Some cosimulation tools enable the designer to choose the computational model, which should perform the simulation of the current design. Ptolemy even supports a free choice of a model for every single component. Other tools allow ....

[Article contains additional citation context not shown here]

S. Edwards, L. Lavagno, E. A. Lee, A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation and Synthesis", Proceedings of the IEEE, Vol.85, No. 3, March 1997.

....here are the core of the method and the remaining research on synthesis and verification are based on existing knowledge and techniques, and are therefore not insurmountable problems. 2. Related Work Many computational models have been described. For a comprehensive overview see Edwards et al. [4]. Very often real time systems are specified by means of concurrent processes, which communicate asynchronously. Such a communication model forms the base for languages as SDL [17, 19] VHDL [18] or SpecCharts [15] While this model serves as a good implementation model, due to its closeness to ....

....argument is a list. The function uses pattern matching. The first pattern matches, when the list is empty. The second pattern matches, when the list is constructed ( by a first element (x) and a rest list (xs) map ( 2) 1,2] 1 2) map ( 2) 2] 2 : 2) 2 : map ( 2) 2 : 4 : [2,4] The type system of Haskell infers the following type for map: map : a b) a] b] This means map is a function, that takes a function as its first argument. This function is characterized by the specification, that it takes one argument of a type a and produces a result of type b. ....

S. Edwards, L. Lavagno, E. A. Lee and A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation and Synthesis", Proc. of the IEEE, March 1997.

....systems include hardware and software components operating together to achieveacommon goal. Realtime embedded systems are often characterized by the need for running several tasks on a limited set of processing units and react continuously to their environment at the speed of the environment[1,2]. These systems are widely used in vehicle control, consumer electronics, communication systems and so on. Design of an embedded system includes design specification, validation and hardware and software synthesis. Embedded software is characterized by tight cost, performance and real time ....

S. Edwards, L. Lavagno, et. al., "Design of Embedded Systems: Formal Models, Validation, and Synthesis," Proc. of the IEEE, Vol. 85, No. 3, p. 366, March1997.

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S. Edwards, L. Lavagno, E. A. Lee, and A. SangiovanniVincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," Proceedings of the IEEE, vol. 85, no. 3, march 1997.

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S. Edwards, L. Lavagno, E. A. Lee and A. SangiovanniVincentelli, "Design of Embedded Systems: Formal Models, Validation and Synthesis" Proc. of IEEE, vol. 85, no. 3, pp. 366-390, Mar 1997

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S. Edward, L. Lavagno, E. Lee, and A. Sangiovanni, "Design of embedded systems: Formal models, validation and synthesis," Proc. IEEE, this issue, pp. 366--390.

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S. A. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of Embedded Systems: Formal Models Validation, and Synthesis. Proceedings of the IEEE, 85(3):366--90, March 1997.

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S. Edwards et al. "Design of Embedded Systems: Formal Models, Validation, and Synthesis ". Proceedings of the IEEE. Vol. 85, No. 3, March 1997.

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S. Edwards, L. Lavagno, E. A. Lee and A. SangiovanniVincentelli, "Design of Embedded Systems: Formal Models, Validation and Synthesis" Proc. of IEEE, vol. 85, no. 3, pp. 366-390, Mar 1997

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S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," in Proc. IEEE, vol. 85, pp. 366-390, March 1997.

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S. Edwards, L. Lavagno, E.A.Lee, and A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," Proceedings of the IEEE, vol. 85, pp. 366--390, March 1997.

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S.Edwards, L. Lavagno, E.A. Lee, A. Sangiovani-Vincentelli, "Design of Embedded Systems: Formal Models, Validation and Synthesis", Proceedings of the IEEE, Vol 85, No. 3, March 1997.

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