Sun Microsystems. The UltraSPARC processor -- technology white paper. http://www.sun.com/microelectronics/whitepapers/UltraSPARCtechnology/.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....by the compiler, but simplifies the implementation effort considerably. 18 Chapter 3 UltraSPARC Case Study To show that performance anomalies constitute a serious problem on commercial microprocessors, I performed a case study of the UltraSPARC Microprocessor, developed by Sun Microsystems [22]. The UltraSPARC is an implementation of the SPARC V9 ISA 1 [27] Through this study, I identified four performance anomalies caused by the design of the architecture. Each of these anomalies was caused by a specific feature of the architecture: next field predictors, fetching logic, grouping ....

Sun Microsystems. The UltraSPARC processor -- technology white paper. http://www.sun.com/microelectronics/whitepapers/UltraSPARCtechnology/.

....like the HP PA800 [17] and the Intel Pentium Pro [18] Figure 3.2 gives the processor parameters used in our simulations. These parameters were chosen to model next generation aggressive processors. The default latencies for the various execution units approximate those for the UltraSPARC [40]. 3.1.3 Variations on the Base Processor The base processor model directly supports the simple implementation of release consistency (RC) Variations on our processor and memory system include a sequentially consistent (SC) processor model, support for hardware controlled non binding ....

Sun Microsystems. The UltraSPARC Processor -- Technology White Paper, 1995.

....architectures. Practical architectures often take advantage of the simple and costeffective shared memory approach with bus backplane interconnects until the number of processors becomes large enough to saturate the bus with memory access requests (Digital Equipment Corporation 1996a; Sun Microsystems, Inc. 1996) These sharedmemory multiprocessors are clustered if it is necessary to design a computer system with more processors than can be efficiently accommodated on a shared memory bus (Digital Equipment Corporation 1996b) Consequently, it is reasonable to expect further development of ....

Sun Microsystems, Inc. 1996. The UltraSPARC processor - technology whitepaper.

....not provided by the R10000, some modern architectures such as PowerPC and the Sun UltraSPARC include support for block loads and stores. For example, UltraSPARC can load or store blocks of floating point registers directly from or to memory without affecting some levels of the cache hierarchy [Sun95] This support affords a unique opportunity to avoid cache pollution from processor block copy. However, implementation concerns such as restrictions on the number of simultaneous block operations may limit the applicability of these operations for achieving internode transfers. 8 Conclusions ....

Sun Microsystems, Inc. The UltraSPARC Processor -- Technology White Paper. http://www.sun.com:80/ sparc/whitepapers/UltraSPARCtechnology/.

....Ypoint[arev 5] ftemp5; Ypoint[arev 6] ftemp6; Ypoint[arev 7] ftemp7; Figure 4. Main loop of the COBRA algorithm. 4 Performance We implemented and experimented with the COBRA algorithm on three processors, the Digital Alpha 21164 (300MHz) 4] 21] the Sun Ultrasparc 2 (200MHz) [14] and the IBM Power2 (RS6000 590) 66MHz) 22] The IBM Power2 we used was a single node of an SP2. It has a 4 way set associative 128KByte primary data cache, with cacheline length of 128 bytes. The data cache miss penalty is 18 cycles and it is write allocate. The TLB has 512 2 way set ....

S. Microsystems. The ultrasparc processor -- technology white paper. http://www.cs.wisc.edu/mscalar/simplescalar.html.

....memory operations and for maintaining consistency constraints. Figure 1 gives the processor parameters used in our simulations. These parameters were chosen to model nextgeneration aggressive processors. The default latencies for the various execution units approximate those for the UltraSPARC [23]. To appear in Proceedings of SPAA 9 (June, 1997) Application Input Size Processors Erlebacher 64 by 64 by 64 cube, block 8 16 FFT 65536 points 16 LU 256 by 256 matrix, block 8 8 MP3D 50000 particles 8 Radix 1024 radix, 512K keys, max 512K 8 Water 343 molecules 16 Figure 2: Application ....

Sun Microsystems. The UltraSPARC Processor -- Technology White Paper, 1995.

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