A. W. Wilson. Hierarchical Cache/Bus Architectures for Shared Memory Multiprocessors. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 244--252, 1987.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....this chapter is joint work with Daniel Sleator; first person plural pronouns (we, our) are used to reflect and acknowledge this. A common design for a large, shared memory multiprocessor system is a network of processors for which each processor or cluster of processors has its own local memory [14, 40, 56]. In such a design, a virtual memory system supports a programming abstraction of memory as a single address space without restrictions on how the pages of this address space are distributed among the local memories. A page of this abstract memory may be stored in just one local memory, or ....

....existing and proposed multiprocessors exhibiting the the Complete topology that are amenable to our algorithms and techniques. These machines include network connected NUMA multiprocessors such as the the BBN Butterfly [14] and IBM RP3 [40] as well as busbased machines such as the Encore Gigamax [56]. Numerous proposed machines such as the NYU Ultracomputer [21] and the directory based cache machine (DASH) at Stanford [36] would also support our algorithms. In contrast, the Tree and U Tree topologies are applicable to far fewer machines. The only existing machine that comes close is the ....

Andrew Wilson Jr. Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors. In Conference Proceedings, 14th International Symposium on Computer Architecture, pages 244--252, Pittsburgh, PA, June 1987. ACM SIGARCH/IEEE Computer Society.

....below them in the tree. Any number of copies of a block are allowed to exist at a time. A read request is typically propagated up the tree until a copy is located; a write typically involves locating and invalidating all of the extra copies by tree traversed and then performing the write. In [30] Wilson proposes the first hierarchical multiprocessor architecture. He suggests modifications to several bus based schemes in order to form a protocol for his proposed hierarchy which uses shared buses of caches to form the tree. He does not, however, consider how his ideas would work on very ....

A. W. Wilson. Hierarchical cache/bus architecture for shared memory multiprocessors. In lth Annual International Symposium on Computer Architecture, pages 244-252, June 1987.

....each one on its own. Overall, we show that using suitable combinations of the techniques, performance can be improved by 4 to 7 times. 1 Introduction Large scale shared memory multiprocessors are expected to have remote memory reference latencies of several tens to hundreds of processor cycles [18, 22, 25, 30]. The large latencies arise partly due to the increased physical dimensions of the parallel machine and partly due to the ever increasing clock rates at which the individual processors operate. These large memory latencies can quickly offset any performance gains expected from the use of ....

....offset any performance gains expected from the use of parallelism. Techniques that can help to reduce or hide these latencies are essential for achieving high processor utilization. To cope with the large latencies, several different architectural techniques have been proposed. Coherent caches [3, 4, 18, 30] allow shared read write data to be cached and significantly reduce the memory latency seen by the processors. Relaxed memory consistency models [1, 5, 8] hide latency by allowing buffering and pipelining of memory references. Prefetching techniques [11, 16, 21, 23] hide the latency by bringing ....

A. W. Wilson, Jr. Hierarchical cache/bus architecture for shared memory multiprocessors. In Proc. Int. Symp. Comput. Arch., pages 244252, June 1987.

....protocol) or invalidates its now stale copy of the data (in an invalidation protocol) When a miss to a block of data is transmitted on the bus, the caches also snoop to see if they have a dirty copy of the data that should be supplied to the requesting processor. Though some have been proposed [20, 8], systems with large numbers of processors that rely on snoopy cache strategies to maintain cache consistency have severe interconnect design constraints due to their reliance on broadcast messages. From the standpoint of interconnect design, a more versatile class of protocols is directory ....

Andrew W. Wilson, Jr. Hierarchical Cache/Bus Archi- tecture for Shared Memory Multiprocessors. In Proc. of the 14th Int. Sym. on Computer Architecture, pages 244-252, June 1987. 12

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A. W. Wilson. Hierarchical Cache/Bus Architectures for Shared Memory Multiprocessors. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 244--252, 1987.

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A. W. Wilson Jr. Hierarchical cache/bus architecture for shared memory multiprocessors. In Proceedings of the Fourteenth International Symposium on Computer Architecture, pages 244-252, June 1987.

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