J. B. Burr and J. Schott, "A 200mv self-test encoder/decoder using Stanford ultra-low power CMOS", ISSCC '9, pp. 84-85, San Fransisco, CA.  Home/Search   Document Not in Database   Summary   Related Articles

....levels of the VLSI design methodology. These techniques include pipelining and parallel processing [6,18] architectural level) precomputation logic [1] logic minimization [25] logic level) optimal coding [7] adia batic computation [2,12] circuit level) device Oreshold voltage ( reduction [5] (device level) and at technological level [11] etc. Estimating the power dissipation (Category 2) for a given architecture is another important problem that has received a lot of attention in recent years [22,23,26,27,33,34] In [22] an information theoretic approach to power estimation was ....

....bit case can be obtained by substituting R = 100 Mb s, W = 150 MHz, cr2 = 10 2 V 2, and CL = 0.5 pF into (6.2) and (6.3) respectively. These lower bounds are Vaa 0.1533 V (6. 4(a) The value of Vdd obtained via the proposed theory is in the same range as the 20 MHz encoder decoder circuit in [5], where Vaa = 0.2 V was employed. As mentioned before, the lower bound in (6.4) is achievable but we do not provide a technique for doing so. B. Circuit Level: A Multi Bit Two Register System For the multi bit case, the total capacity of a M bit word to word link is given by M J C = E ....

J. B. Burr and J. Schott, "A 200mv self-test encoder/decoder using Stanford ultra-low power CMOS", ISSCC '9, pp. 84-85, San Fransisco, CA.

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