S. Heo and K. Asanovic, "Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction," June 2002, pp. 316 --319.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....technique [16] dual ) to reduce subthreshold leakage current in the integer functional units (FUs) of a general purpose processor. We focus on domino logic dual circuits because domino logic has both superior speed and area characteristics as compared to static CMOS logic circuits [1, 10, 13, 16]. We restrict the analysis to the integer FUs because it is these units that are most heavily utilized. Some domino logic designs have a sleep mode in which the circuit expends very little static energy. However, due to the energy cost of entering this mode, it has thus far been proven useful ....

....switching energy is the leakage factor V n)o qrq o q Us . Since (3) models the energy relative , the relatively small values of the other factors means the leakage factor has the greatest impact. We note here that from a similar circuit characterization by Heo and Asanovic [10] we estimate from the data in the paper that their implementation of a Hans Carlson adder circuit in 70 nm technology has a leakage factor that is comparable to our result, between AtUs uV As . 3.1 Analysis The analytical model permits quick exploration of the parameter space ....

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S. Heo and K. Asanovic. Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction. In Symposium on VLSI Circuits, June 2002.

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S. Heo and K. Asanovic, "Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction," June 2002, pp. 316 --319.

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