D. Das and N. A. Touba, "Reducing test data volume using external /LBIST hybrid test patterns," in Proc. Int. Test Conf., Atlantic City, NJ, 2000, pp. 115--122.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....the test application time to some extent [8] Similarly, several test data volume reduction techniques have also been suggested in the literature. A recently introduced technique utilizes a hybrid of automatic test pattern generation (ATPG) and built in self test (BIST) to reduce data volume [9]. Another technique involves hybrid BIST based on weighted pseudo random testing [10] A technique based on compression decompression using virtual scan chain has also been suggested [11] Most of these techniques suggested in the literature do not address the needs for embedded cores used in ....

D. Das and N. A. Touba, "Reducing test data volume using external/LBIST hybrid test patterns," in Proc. Int. Test Conf., October 2000, pp. 115-122.

....chains reduces both test application time and test data volume by 46.5 , when compared with a conventional transition test set computed by COM. A number of ideas on reducing test data volume and test application time for single cycle scan tests have been presented in the literature[2] 4] 5] 3] [23] [22] These work assume that between 5 10 of the bits are fully specified. Unspecified bits are filled to detect the easy to detect faults. Different codes to compress the information in the tester and decompressing them on chip [2] 5] 23] or using partitioning and applying similar patterns ....

....have been presented in the literature[2] 4] 5] 3] 23] 22] These work assume that between 5 10 of the bits are fully specified. Unspecified bits are filled to detect the easy to detect faults. Different codes to compress the information in the tester and decompressing them on chip [2] 5] [23] or using partitioning and applying similar patterns to the different partitions [3] 22] have been proposed. The techniques proposed here complements the work on compressing individual vectors. The technique of Section 3 can be used with all the stuck at test compression technique described in ....

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D. Das and N. A. Touba, "Reducing test data volume using external/LBIST hybrid test patterns," IEEE International Test Conference, 2000, pp. 115122.

....by BIST. So a straightforward hybrid BIST approach where pseudo random vectors are applied with BIST hardware followed by deterministic vectors from the external tester, can only achieve a limited reduction in tester storage requirements, generally not an order of magnitude reduction. In [Das 00] a hybrid BIST approach was proposed where some of the scan chains in a STUMPS architecture are filled with deterministic test data from the tester while the rest of the scan chains are filled from the pseudorandom pattern generator (PRPG) The set of scan chains receiving deterministic data ....

Das, D., and N.A. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns," Proc. of International Test Conference, pp. 115-122, 2000.

....that can be achieved on the transformed test set using statistical coding. ATPG algorithms for producing test vectors that can more effectively be compressed using statistical codes have been described in [20] Test vector compression based on hybrid BIST techniques have been described in [10], 29] and [27] A novel scheme of test vector compression using an embedded processor is described in [25] In [13] a test vector compression technique based on geometric primitives is proposed. Very recently, a new line of research has focused on compressing test data volume while optimizing ....

D. Das and N. A. Touba, "Reducing test data volume using external /LBIST hybrid test patterns," in Proc. Int. Test Conf., 2000, pp. 115--122.

.... scan circuits using selective Huffman coding is presented in [14] Chandra and Chakrabarty have proposed test vector compression techniques based on Golomb codes [3, 4] and frequency directed run length (FDR) codes [5] Test vector compression based on hybrid BIST techniques have been described in [6] and [15] In [8] a test vector compression technique based on geometric primitives is proposed. In this technique, test vectors are optimally reordered and divided into blocks and then encoded based on geometric shapes. Although the technique achieves high compression, the authors have not ....

D. Das and N.A. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns," in Proc. of International Test Conference, 2000, pp. 115--122.

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D. Das and N. A. Touba, "Reducing test data volume using external /LBIST hybrid test patterns," in Proc. Int. Test Conf., Atlantic City, NJ, 2000, pp. 115--122.

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D. Das and N.A. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns," Proc. Int'l Test Conf., pp. 115-122, 2000.

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D. Das and N. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid test patterns," in Proc. Int. Test Conf. (ITC'00), pp. 115-122, 2000.

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D. Das and N. A. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns," in Proceedings IEEE International Test Conference (ITC), pp. 115--122, IEEE Computer Society Press, Oct. 2000.

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Das, D., and N.A. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns," Proc. of International Test Conference, pp. 115-122, 2000.

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