B. Rychlik, J. Faistl, B. Krug, and J. P.Shen. E#cacy and performance impact of value prediction. In International Conference on Parallel Architectures and Compilation Techniques, pages 148--154, Oct 1998. 187  Home/Search   Document Not in Database   Summary   Related Articles   Check

....increases the code size. Applying speculation to loads that are unlikely to be predicted correctly will incur a misspeculation penalty and slow down program execution. The recent load value prediction literature proposes complex predictors that combine multiple basic predictors (hy brids) [8, 25, 31] and incorporate confidence estimators to dynamically decide which loads are worth predicting and with which predictor [5, 7, 9, 20, 24] The confidence estimators try to filter out loads that would be mispredicted since mispredictions lower program performance. While modern load value predictors ....

....frequent than true stride behavior [6, 19] In particular, alternating sequences occur relatively often when variables toggle between two values. The finite context method predictor fcm [26, 27] computes a hash value out of the last four values of a load using a select fold shift xor function [24, 25, 26] to index the predictor s second level table. This table stores the values that follow every seen sequence of four values (modulo the table size) Since the table is shared, load instructions can communicate information to one another in this predictor. Hence, after observing a sequence of load ....

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B. Rychlik, J. Faistl, B. Krug, and J. P. Shen. E#cacy and performance impact of value prediction. In Proceedings of the international conference on parallel architectures and compilation techniques, 1998.

....which are discussed below. To address the drawbacks, we study postdecode prediction as a front end alternative, and latency and energy aware prediction as a back end option. 2. 1 At fetch Value Prediction Performing value prediction at instruction fetch is a commonly assumed implementation [5, 10, 14, 22]. In a typical processor, an instruction address can be sent to the fetch logic each cycle. This same fetch address is used to access the value predictor. Based on the fetch PC, the value predictor generates predictions for all of the instructions being fetched in that cycle. This imposes two ....

....load value prediction only allows for 6.2 speedup for these benchmarks. 5. RELATED WORK There have been many strategies proposed for data value prediction. The primary ones include last value prediction [14, 15] stride prediction [9, 11] context prediction [24, 30] and hybrid prediction [22, 30]. More recently, hybrid predictors with the ability to dynamically classify instructions have been evaluated [12, 23] In this work, we look primarily at advanced hybrid predictors with a last value predictor, stride predictor and a context predictor, but without the dynamic classification ....

B. Rychlik, J. Faistl, B. Krug, and J. P.Shen. E#cacy and performance impact of value prediction. In Compilation Techniques, pages 148--154, Oct 1998.

....ports. The precise reason is di#cult to isolate since performance benefits of value prediction are based on a combination of factors, such as misprediction rate, prediction confidence, update frequency, varying rewards for correct predictions, and varying penalties for mispredictions [18, 34]. Table 4: Analysis of Value Prediction E#ectiveness VP Tint MP Rate 7.57 7.84 4.03 8.89 5.37 5.55 17.51 SVP 2 MP Rate 13.00 13.57 5.21 16.26 8.41 8.26 29.27 VP Tint Coverage 98.43 84.20 94.64 95.98 95.56 99.93 99.71 SVP 2 Coverage 99.18 77.42 69.36 82.39 77.28 98.78 99.34 parser perlbmk ....

B. Rychlik, J. Faistl, B. Krug, and J. P.Shen. E#cacy and performance impact of value prediction. In International Conference on Parallel Architectures and Compilation Techniques,Oct 1998.

....which are discussed below. To address the drawbacks, we study PostDecode prediction as a front end alternative and Latency and Energy Aware (LEA) prediction as a back end option. 2. 1 At Fetch Value Prediction Performing value prediction at instruction fetch is a commonly assumed implementation [4, 9, 13, 22]. In a typical processor, an instruction address can be sent to the fetch logic each cycle. This same fetch address is used to access the value predictor. Based on the fetch PC, the value predictor generates predictions for all of the instructions being fetched in that cycle. This imposes two ....

....and exclusively result producing instructions) The fast instruction filter identifies quickly executing instructions. Quickly executing is defined as instructions that execute before a value prediction becomes available. The useless filter is based on the observation of useless predictions [22] and prevents instructions whose predictions are not consumed from doing more predictions. The filters are driven by history based counters. The counters for the fast filter and useless filter are the common two bit saturating counters found in many types of speculative hardware. They are ....

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B. Rychlik, J. Faistl, B. Krug, and J. P.Shen. E#cacy and performance impact of value prediction. In International Conference on Parallel Architectures and Compilation Techniques, pages 148--154, Oct 1998.

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B. Rychlik, J. Faistl, B. Krug, and J. P.Shen. E#cacy and performance impact of value prediction. In International Conference on Parallel Architectures and Compilation Techniques, pages 148--154, Oct 1998. 187

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