A. Deng, "Power Analysis for CMOS/BiCMOS Circuits," 1994 International Workshop on Low Power Design, Napa Valley, CA, pp. 3-8, April 1994. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Vector Generation for Power Supply Noise Estimation and.. - Jiang, Cheng (2001) (Correct)
....of each individual block as a major factor of fitness. In the meantime, we also include the current of the entire design into fitness. This is because current from other blocks also contributes to the power supply noise of the target block. We use an approximate but efficient approach proposed in [5] and [25] to transistor level simulation for extracting the peak current. Also, during the transistor level simulation, power supply network and thus the power supply noise is ignored to speed up the simulation. In other words, we simulate only the transistor netlist and assume constant voltages ....
A.-C. Deng, "Power analysis for CMOS/BiCMOS circuits," in Int. Symp. Low-Power Electronics and Design (ISLPED), 1994, pp. 3--8.
VIP - An Input Pattern Generator for Identifying Critical.. - Jiang, Young, al. (1999) (Correct)
....patterns for simulation of the voltage drops has become a necessary step in the entire design cycle. Recently, several Genetic Algorithm based (GA based) techniques have been proposed to generate the input patterns for identifying the maximam instantaneous current [4] maximum power dissipation [ 1 ], and maximum voltage drop [5] Through iterativety generating the new test patterns for simulation based on the good property of the current patterns, they produce tight lower bounds for these problems. In such a way, however, certain functional blocks whose current has little contribution to ....
....of the entire design into fitness. This is because current from other blocks also contributes to the voltage drop of the target block. We perform transistor level simulation to extract the peak current based on the simulation results. We use an approximate but efficient approach proposed in [11][1] to transistor level simulation. During the transistor level simulation, power supply network voltage drops are ignored to speed up the simulation. In other words, we simulate only the transistor neflist and assume constant voltages at power buses during the simulation. The model for this speed up ....
A.-C. Deng, "Power Analysis for CMOS/BiCMOS Circuits," International Symposium on Low-Power Electronics and Design (1SLPED), pp. 3-8, 1994.
Leakage Power Reduction for Reactive Computation - Favalli, Metra (Correct)
....is the clock frequency. As a matter of fact, the terms (a) and (b) depend, in an almost complex way, on the kind of gate input and output activity, including an important contribution due to glitches [15] Nevertheless, it is important to notice that several simulation based (at either the logic [16, 17, 18] or the electrical level [19] or pattern independent (probabilistic [20, 21] or symbolic [22] techniques can be used to evaluate P gate and, therefore, P active once the kind of input activityatC is known. Since the only differences between the standard and the proposed implementation is due to ....
A. Deng, "Power analysis for CMOS/BiCMOS circuits," in IEEE Int. Workshop on Low Power Design, pp. 3 -- 8, 1994.
Design Technologies for Low Power VLSI - Pedram (1997) (2 citations) (Correct)
....and are not suitable for large, cell based designs. In addition, it is difficult to generate a compact stimulus vector set to calculate accurate activity factors at the circuit nodes. The size of such a vector set is dependent on the application and the system environment [54] PowerMill [18] is a transistor level power simulator and analyzer which applies an event driven timing simulation algorithm (based on simplified table driven device models, circuit partitioning and single step nonlinear iteration) to increase the speed by two to three orders of magnitude over SPICE. ....
C. Deng. " Power analysis for CMOS/BiCMOS circuits. " In Proceedings of the 1994.
Module Assignment for Low Power - Chang, Pedram (1996) (6 citations) Self-citation (Power) (Correct)
.... equation as follows: PFU #0#5###V #f#sw #op1#op 2# (3) where V is the supply voltage, f is the clock frequency, and the proportionality constant # (which represents the physical capacitance of the functional unit) is calculated for each functional unit using circuit or gate level simulation [Deng94][BuNa93] and curve fitting. Obviously this proportionality constant depends on the module type, input data width, technology and logic style used and internal module structure. Equation ( 3) is the basis of all macro modeling techniques for power estimation and has been used in the works of ....
C. Deng, Power Analysis for CMOS/BiCMOS circuits. In Proceedings of the 1994 International Workshop on Low Power Design, pp. 3-8, April 1994.
Low Power Architectural Design Methodologies - Landman (1994) (22 citations) (Correct)
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A. Deng, "Power Analysis for CMOS/BiCMOS Circuits," 1994 International Workshop on Low Power Design, Napa Valley, CA, pp. 3-8, April 1994.
Advanced Power Estimation Techniques - Pedram (1997) (3 citations) (Correct)
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C. Deng. "Power analysis for CMOS/BiCMOS circuits," Proceedings of 1994.
Power Estimation and Optimization at the Logic - Level Massoud Pedram (Correct)
No context found.
C. Deng. Power analysis for CMOS/BiCMOS circuits. In Proceedings of the 1994.
Stratified Random Sampling for Power Estimation - Chih-Shun Ding Qing (1996) (5 citations) (Correct)
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C. Deng. Power analysis for CMOS/BiCMOS circuits. In Proceedings of 1994.
Unknown - (Correct)
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C. Deng, "Power Analysis for CMOS/BiCMOS Circuits", in Proceedings of International Workshop on Low Power Design, pp. 3-8, April, 1994
Low Power CAD: Trends and Challenges - Massoud Pedram Department (Correct)
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C. Deng. Power analysis for CMOS/BiCMOS circuits. In Proceedings of the 1994.
CAD for Low Power: Status and Promising Directions - Pedram (1995) (Correct)
No context found.
C. Deng. Power analysis for CMOS/BiCMOS circuits. In Proceedings of the 1994.
Layout Techniques Supporting the Use of Dual Supply.. - Shan-Jih Shieh.. (Correct)
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Deng, C. Power analysis for CMOS/BiCMOS circuits. Proc. Int. Workshop on Low Power Design, Apr. 1994, pp. 3-8.
Gate-Level Power and Current Simulation of CMOS.. - Bogliolo, Benini.. (1997) (1 citation) (Correct)
No context found.
A. Deng, "Power analysis for CMOS/BiCMOS circuits," in Proc. Int. Workshop on Low Power Design, 1994, pp. 3--8.
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