N. Nicolici and B. M. Al-Hashimi, "Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths", Proc. of IEEE Int. Test Conference (ITC), pp. 662-671, Oct. 2000. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
Power Constrained Preemptive TAM Scheduling - Erik Larsson And (2002) (1 citation) (Correct)
.... Recently TAM scheduling, a special case of test scheduling, has gained interest [7,9] An important issue then is the wrapper used to connect the cores to the TAM [11,15,16,17] Techniques have also been proposed to reduce test power dissipation allowing testing at higher clock frequencies [6,19,21]. In this paper, we combine preemption based test scheduling [8] and scan chain partitioning [1] to a preemptive TAM scheduling technique under power constraint, which we modelled as a Bin packing problem. We also outline a flexible power conscious test wrapper, which is useful to (1) control the ....
N. Nicolici and B. M. Al-Hashimi, "Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths", pp. 662-671, Atlantic City, NJ, Oct. 2000.
Power Minimisation Techniques for Testing Low Power VLSI Circuits - Nicolici (2000) (2 citations) (Correct)
....performance degradation, volume of test data, and fault escape probability over the traditional BIST embedding methodology described in Section 1.3.2. Chapter 6 shows how power dissipation during test application is minimised at the register transfer level of abstraction of the VLSI design flow [141]. The three dimensional testable design space described in Figure 1.13 from Section 1.4 is explored using novel power conscious test synthesis and test scheduling algorithms at the expense of low overhead in computational time. Finally, conclusions and directions for future research are given in ....
....of low overhead in computational time. Finally, conclusions and directions for future research are given in Chapter 7. The previously outlined contributions in Chapters 3, 4, 5, and 6, and summarised in the final Chapter 7 have resulted in original work published or submitted for publication [139, 140, 141, 142, 143, 144, 145]. Motivation and Previous Work Personal mobile communications and portable computing systems are the fastest growing sectors of the consumer electronics market. The electronic devices at the heart of such products need to dissipate low power, in order to conserve battery life and meet packaging ....
N. Nicolici and B.M. Al-Hashimi. Power conscious test synthesis and scheduling for BIST RTL data paths. In Proc. IEEE International Test Conference (ITC 2000.
Multiple Scan Chains for Power Minimization During Test.. - Nicolici, Al-Hashimi (2002) (1 citation) Self-citation (Nicolici Al-hashimi) (Correct)
....proposed solutions for solving problems (i) iii) of section 1.1. Problem (i) To overcome the problem of high power dissipation during test application at the system level , numerous power constrained test scheduling algorithms have been proposed under built in self test (BIST) environment [1, 6 11]. The approach in [1] schedules the tests under power constraints by grouping and ordering based on floorplan information. A further exploration in the solution space of the scheduling problem is provided in [6] where a resource graph formulation for the test problem is given and tests are ....
....table minimization problem applied in [6] which are well known NP hard problems, the solution proposed in [7] uses the left edge algorithm and tree growing technique as an heuristic for the block test scheduling problem. Several solutions for scheduling tests under power and area constraints [8 11] have recently been proposed. However, all the previous approaches assume BIST environment which trades off high test area overhead and test application time at the expense of lower power dissipation during testing. 2 Problem (ii) A new ATPG tool [5] was proposed to overcome the low correlation ....
N. Nicolici and B. Al-Hashimi, "Power conscious test synthesis and scheduling for BIST RTL data paths," in Proc. IEEE International Test Conference (ITC
Power Constrained Preemptive TAM Scheduling - Erik Larsson And (2002) (1 citation) (Correct)
No context found.
N. Nicolici and B. M. Al-Hashimi, "Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths", Proc. of IEEE Int. Test Conference (ITC), pp. 662-671, Oct. 2000.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC