Chin-Liang Wang, Chee-Ho Wei, and Sin-Horng Chen. "Efficient bit-level systolic array implementation of FIR and IIR digital filters." IEEE Journal on Selected Areas in Communications, 6(3):484--493, April 1988.  Home/Search   Document Not in Database   Summary   Related Articles

....multipliers as if 512 multipliers had been used with a clock rate equal to the sample rate. 6. 4 Bit Level Systolic Array An approach which has proven to be a very efficient VLSI implementation at MIT Lincoln Laboratory [Son] is a fully efficient bit level systolic structure by Chin Liang Wang [WWC88] With this technique, single bit processors compute each tap s multiplication partial products and accumulate tap outputs together in a systolic array. As inputs propagate through the array, filtered outputs are produced. The systolic nature of this approach lends itself well to Mac 0 Mac1 ....

....connections between CLBs. The configuration of this array and the logic required to implement each cell is shown in Figure 6.6. Since this technique did not turn out to be efficient in a FPGA architecture (see Section 7. 3) the derivation if its structure will not be included here (see [Son, WWC88] for more information) It is presented to show the differences between architectures optimized for a FPGA s coarsegrained structure versus architectures optimized at the transistor level for a VLSI approach. Figure 6.5: Eight Taps Per MAC FIR Filter 0 1 0 1 Reg h[8 15] Reg Banks Reg ....

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Chin-Liang Wang, Chee-Ho Wei, and Sin-Horng Chen. "Efficient bit-level systolic array implementation of FIR and IIR digital filters." IEEE Journal on Selected Areas in Communications, 6(3):484--493, April 1988.

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