G. Chien, private communication. [In a low power ADC application, gate capacitance is poorly modelled by HSPICE with the level 28 model, especially for Vdsat < 100mV.] 152  Home/Search   Document Not in Database   Summary   Related Articles

....biasing was used. 1. BSIM 3 models in development at U.C. Berkeley have passed most of these, but have not passed the weak inversion output conductance problem. HUI94] 2. Gate capacitance in moderate inversion is an important, poorly modelled, effect in some low power gain block applications [CHIE94] 6.3 Inputs for DSYN 106 6.3.3 Temperature Variation All semiconductor products are specified for an operating temperature range, and designs are built to function across a range of junction temperatures. Device models include temperature effects, and circuits are simulated at the extremes of ....

G. Chien, private communication. [In a low power ADC application, gate capacitance is poorly modelled by HSPICE with the level 28 model, especially for Vdsat < 100mV.] 152

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