Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 26--37. ACM Press, 1998.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....corner of Figure 2. Generally, for arbitrary P and Q,itisimpossible to decide statically whether they will access same address with same value. The Venn diagram at the bottom of Figure 2 shows the relationship between these three categories. Both hardware [18, 23, 31, 36] and software techniques [25, 29, 24, 4, 6] have been proposed to detect and remove redundant memory operations. In their dynamic instruction reuse work [31] Sodani et al. propose to use hardware lookup tables to store operation input and result. A redundant operation is detected by matching input against lookup table entries. If there is ....

....most algorithms only deal with unambiguous scalar values. Aliased memory operations cause the algorithms to use worst case assumptions, i.e. allscalar values related to memory would be killed by an aliased store. On the other hand, work on register promotion focuses solely on memory redundancy [25, 24, 29]. As our experimental results show, these two kinds of redundancy interact, so detecting one often allows the compiler to detect the other. The published algorithms for register promotion work from a lexical notion of identity, rather than from a value based identity.Thevalue based approach taken ....

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In on Programming Language Design and Implementation,pages 26--37, 1998.

....to graph information. It is simple. A bestiary of new OE like functions have been introduced in the past decade, including , fl , and j functions in [5, 43] and functions in [24] interprocedural OE functions in [26] and functions in [9] and j functions in [14] and functions in [27], among others.Some of these are orthogonal to our work the techniques of [24] can be used to extend SSI form to explicitly parallel source languages, and those of [9] to languages with local variable aliasing (absent in Java) Our goal is to achieve minimal conceptual complexity in SSI form; ....

....cannot handle backward dataflow analysis. Johnson and Pingali note this, and suggest anticipatability as an example of a backwards dataflow analysis where their dependence flow graph representation betters SSA form [20] Lo et al. suggest the use of an SSU form to address much the same issue [27]. There are in fact many analyses where both use and definition information is utilized, and where dataflow in both forward and reverse directions occurs. SSI form is able to handle both of these cases, as we demonstrate in section 6.1. Dhamdhere [12] quite correctly states that Cytron s ....

R. Lo, F. Chow, R. Kennedy, S.-M. Liu, and P. Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In Language Design and Implementation (PLDI), pages 26--37, Montreal, Canada, June 1998.

....as shown in Figure 1. The SGI MIPSpro compiler is an industrystrength highly optimizing compiler. It implements a broad range of optimizations, including interprocedural analysis and optimization (IPA) loop nest optimization and parallelization (LNO) 18] and SSA based global optimization (WOPT) [2, 11] at high level. It also has an efficient backend including software pipelining, integrated global and local scheduler(IGLS) 12] and efficient global and register allocators (GRA and LRA) 3] The legality of loop nest optimizations listed in Section 2 depends on dependence analysis [20] The SGI ....

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In Proc. of the ACM SIGPLAN '98 Conf. on Programming Language Design and Implementation, pages 26--37, Montreal, Que., Jun. 17--19,

....as shown in Figure 1. The SGI MIPSpro compiler is an industrystrength highly optimizing compiler. It implements a broad range of optimizations, including interprocedural analysis and optimization (IPA) loop nest optimization and parallelization (LNO) 18] and SSA based global optimization (WOPT) [2, 11] at high level. It also has an efficient backend including software pipelining, integrated global and local scheduler(IGLS) 12] and efficient global and register allocators (GRA and LRA) 3] The legality of loop nest optimizations listed in Section 2 depends on dependence analysis [20] The SGI ....

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In Proc. of the ACM SIGPLAN '98 Conf. on Programming Language Design and Implementation, pages 26--37, Montreal, Que., Jun. 17--19,

....and backward data flow dependencies for a variety of purposes viz. Partial Redundancy Elimination (PRE) 5, 9, 22, 44, 47, 54] and related optimizations [6, 16, 39, 53] Code Hoisting and Strength Reduction [15, 17, 21, 26, 29, 30, 36] Live Range Characterisation and Register Assignment [14, 41]. Dead Code Elimination [4, 38] Communication Placement [25, 27] Shrink Wrapping of Procedure Calls [8] Redundant Array Bound Checks Elimination [40] Compilation for Distributed Memory [1] Data flow analysis for some of the above optimizations involves a sequence of separate ....

R. Lo, F. C. Chow, R. Kennedy, S. M. Liu, and P. Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In Proceesings of ACM SIGPLAN '98 Conference on Programming Language Design and Implementation, pages 26--37, 1997. Also Published as SIGPLAN Notices, 33(5).

.... optimizations that take advantage of knowledge of the data flow impact on precise exceptions, as well as to establish a lower bound for PRE style optimizations in which precise exception semantics are not enforced (with the loose results) Several recent papers have focused on register promotion [57 59]: the identification of program regions in which memory allocated values can be cached in registers. These techniques also address the issue of eliminating redundant loads and stores by selectively promoting values from memory into registers. Our approach differs in that we perform analysis and ....

Lo R, Chow F, Kennedy R, Liu S-M, Tu P. Register promotion by sparse partial redundancy elimination of loads and stores. Proceedings of the ACM Conference on Programming Language Design and Implementation, Montreal, Canada, June 1998. ACM SIGPLAN Notices 1998; 33(5):26--37.

....Figure 6 presents the reduction in number of dynamic loads for each benchmark with respect to the original baseline. As it can be seen, all programs do show improvements typically around 5 , with some rather better cases such as m88ksim and compress. Comparing our results to Table 2 in Lo et al. [17], we can see that we achieve less benefits. However, we believe the reason for that is that we are working on final machine code while they were measuring reduction in dynamic loads before code generation and register allocation. Factoring this in, our results are very much in line with those ....

....see that we achieve less benefits. However, we believe the reason for that is that we are working on final machine code while they were measuring reduction in dynamic loads before code generation and register allocation. Factoring this in, our results are very much in line with those presented in [17], yet we do not have the advantage of high quality alias analysis as they do. The results show also that working only on EBBs is not enough to catch the close redundancy we presented in Section 2. Except maybe for perl and vortex, LRE applied to EBBs yields a small reduction in dynamic loads. By ....

R. Lo, F. Chow, R. Keneddy, S.-M. Liu, and P. Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation, pages 26--37, Montreal, Canada, June 17--19 1998.

....optimizations [29] post link time optimizations [30] and run time optimizations [31, 32, 33, 34, 35, 36] Profiling is often advocated as a way to provide this run time information to the compiler. Profiling can increase the performance gain or reduce the code expansion of optimizations [37, 38, 39, 40, 41, 42, 43]. Virtual machines naturally provide this information to the compiler. When the compiler is integrated within a VM, profile information specific to the particular execution being optimized is provided. This allows our virtual architecture model to adjust the binary for each execution of the ....

Raymond Lod, Fred Chow, Robert Kennedy, ShinMing Liu, Peng Tu, "Register Promotion by Sparse Partial Redundancy Elimination of Loads and Stores," Prog. Lang. Design and Impl., pp. 26-37, June 1998.

....a register reference. In the example, register promotion is not immediately applicable because load a4 is not redundant on all paths. Such partial reuse can be compensatedby hoisting a copy of the load along path p3 . Commonly, the hoisting is formulated as partial redundancy elimination (PRE) [26, 28, 35]. is a2 = a4 along path p2 is a1 = a4 along path p1 is a0 = a4 hoist load a4 along path p3 3 Program transformation: 2 Alias analysis: 1 Load reuse analysis: load store a4 a0 path p1 path p2 path p3 load a1 store a2 Detecting reuse is profitable even when register promotion is prevented ....

..... In this paper, T is the partial redundancyelimination (PRE) 10, 24,28] PRE is a code motion transformation that can exploit reuse even when it exists only on a subset of execution paths incoming to the redundant load. Therefore, PRE has become the basis of modern register promotion techniques [6, 14, 26, 35]. Unfortunately, detecting load reuse is in general undecidable [31] and so no compile time PRE complete load reuse analysis exists. Therefore, we use an empirical, run time analysis that measures the reuse in the program as the program executes. In order to provide a close approximation of ....

[Article contains additional citation context not shown here]

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In Proceedings of the ACM SIGPLAN'98 Conference on Programming Language Design and Implementation (PLDI), pages 26--37, Montreal, Canada, 17--19 June 1998.

....are generated using the optimizer WOPT, a component of the Silicon Graphics MIPSpro Compiler Suite. WOPT is an intraprocedural global optimizer that uses SSA as its internal program representation for performing all its optimizations [Liu et al. 1996; Chow et al. 1996; Kennedy et al. 1998; Lo et al. 1998]. The SSAPRE phase in WOPT incorporates the practical implementation techniques described in Section 5. For our measurements the benchmarks were compiled at the optimization level O2, in which only intraprocedural analyses and optimizations are performed. Our implementation of SSAPRE ....

....first use of SSA to solve data flow problems related to expressions in the program. This work opens up the possibility to solve other expressionbased data flow problems by representing them in the form of factored dependency edges and performing data flow analyses on the resulting sparse graph. In [Lo et al. 1998], we have applied this approach in performing load and store placement optimizations. Other candidate optimizations for using this framework are code hoisting, register shrink wrapping [Chow 1988] and live range shrinking. PRE has traditionally provided the context for integrating additional ....

[Article contains additional citation context not shown here]

Lo, R., Chow, F., Kennedy, R., Liu, S., and Tu, P. 1998. Register promotion by sparse partial redundancy elimination of loads and stores. In Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation.

No context found.

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 26--37. ACM Press, 1998.

No context found.

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 26--37. ACM Press, 1998.

No context found.

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 26--37. ACM Press, 1998.

No context found.

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 26--37. ACM Press, 1998.

No context found.

R. Lo, F. Chow, R. Kennedy, S.-M. Liu, and P. Tu. Register promotion by sparse partial redundancy elimination of loads and stores. pages 26--37. 1998 ACM SIGPLAN Conference on Programming Language Design and Implementation.

No context found.

R. Lo, F. Chow, R. Kennedy, S. Liu, and P. Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In Proc. PLDI'98, pages 26-- 37, 1998.

No context found.

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pages 26--37. ACM Press, 1998.

No context found.

R. Lo, F. Chow, R. Kennedy, S.-M. Liu, and P. Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In Language Design and Implementation (PLDI), pages 26-37, Montreal, Canada, June 1998.

No context found.

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Liu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), pages 26--37, Montreal, Canada, 17--19 June 1998. 153

No context found.

Raymond Lo, Fred Chow, Robert Kennedy, Shin-Ming Lu, and Peng Tu. Register promotion by sparse partial redundancy elimination of loads and stores. In Proceedings of the SIGPLAN '98 Conference on Programming Language Design and Implementation, pages 26--37, June 1998.

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