| Annette Bunker and Ganesh Gopalakrishnan. Verifying a Virtual Component Interface-based PCI Bus Wrapper Using an LSC-Based Speci - cation. Technical Report UUCS-02-004, University of Utah, School of Computing, 2002. |
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Annette Bunker and Ganesh Gopalakrishnan. Verifying a Virtual Component Interface-based PCI Bus Wrapper Using FormalCheck and an LSC-based Specification. Technical Report UUCS-02-004, University of Utah, 2002.
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Annette Bunker and Ganesh Gopalakrishnan. Verifying a Virtual Component Interface-based PCI Bus Wrapper Using FormalCheck. Technical Report UUCS-01-006, University of Utah, 2001.
....queues, the wrapper tries to generate an extra, garbage transaction. Removing the optimization, forcing the PCI state machine to travel through a recovery state before testing the status bits, solves the problem. The experimental verification found all the bugs reported in the original project [BG01b] except the buggy bug fix. We had the advantage of experience in the second project and the bug was avoided Property State Vars Time Memory 1 71 4 min, 9 sec 481 MB 2 71 4 min, 54 sec 438 MB 3 67 2 min, 40 sec 473 MB 4 143 5 143 6 87 7 87 4 78 28 min, 56 sec 563 ....
Annette Bunker and Ganesh Gopalakrishnan. Verifying a virtual component interface-based pci bus wrapper using formalcheck. Technical Report UUCS-01-006, University of Utah, June 2001.
....module which translates the VCI transactions into the equivalent transactions on any bus of the integrator s choice. In this manner, the IP provider can design a core without knowing which bus the integrator will chose. Our VCI wrapper for PCI consists of eight fifos and six state machines [5], as shown in Figure 1. Each fifo queues one field of the request or response, while earlier transactions proceed on the buses. The address, byte enables (be) command (cmd[1:0] write data (wdata[31:0] and end of packet (eop) fifos contain the input transaction information from the VCI, as ....
....Subsection IV C explains the constraints needed to complete the model checking. Subsection IV D compares and contrasts the properties we verified. We discuss the issues found with the design in this case study in Subsection IV E. We treat each verification project more completely elsewhere [4] [5]. A. Specifications The specification used for each verification of the wrapper model is the primary source for the differences between the two projects. We derive the specification used in the first verification project from study of the VCI standard document, the PCI standard document and our ....
Annette Bunker and Ganesh Gopalakrishnan. Verifying a Virtual Component Interface-based PCI Bus Wrapper Using FormalCheck and an LSC-based Specification. Technical Report UUCS-02-004, University of Utah, 2002.
....and Subsection IV C explains the constraints needed to complete the model checking. Subsection IV D compares and contrasts the properties we verified. We discuss the issues found with the design in this case study in Subsection IV E. We treat each verification project more completely elsewhere [4], 5] A. Specifications The specification used for each verification of the wrapper model is the primary source for the differences between the two projects. We derive the specification used in the first verification project from study of the VCI standard document, the PCI standard document and ....
Annette Bunker and Ganesh Gopalakrishnan. Verifying a Virtual Component Interface-based PCI Bus Wrapper Using FormalCheck. Technical Report UUCS-01-006, University of Utah, 2001.
....queues, the wrapper tries to generate an extra, garbage transaction. Removing the optimization, forcing the PCI state machine to travel through a recovery state before testing the status bits, solves the problem. The experimental verification found all the bugs reported in the original project [BG01b] except the buggy bug fix. We had the advantage of experience in the second project and the bug was avoided Property State Vars Time Memory 1 71 4 min, 9 sec 481 MB 2 71 4 min, 54 sec 438 MB 3 67 2 min, 40 sec 473 MB 4 143 5 143 6 87 7 87 4 78 28 min, 56 sec 563 ....
Annette Bunker and Ganesh Gopalakrishnan. Verifying a virtual component interface-based pci bus wrapper using formalcheck. Technical Report UUCS-01-006, University of Utah, June 2001.
....out a verification effort relating to a design derived from the VCI standard. Our wrapper was designed in Verilog and the verification was carried out using FormalCheck 2 . The VCI complaint half of the wrapper met the BVCI specification. Detailed verification results are reported elsewhere [BG01] 3 . For the purposes of the current report, however, we focus on the lessons learned from this case study. 2 FormalCheck is a trademark of Lucent Technologies and Cadence Design Systems and is licensed to universities free of charge upon request: ftp.cadence.com formalcheck. 3 Complete ....
Annette Bunker and Ganesh Gopalakrishnan. Verifying a virtual component interface-based PCI bus wrapper using FormalCheck. Technical report, University of Utah, June 2001.
No context found.
Annette Bunker and Ganesh Gopalakrishnan. Verifying a Virtual Component Interface-based PCI Bus Wrapper Using an LSC-Based Speci - cation. Technical Report UUCS-02-004, University of Utah, School of Computing, 2002.
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