S. Sastry, R. Bodk, and J. Smith. Rapid Profiling via Stratified Sampling. In Annual International Symposium on Computer Architecture, pages 278--289, July 2001.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....such as basic block frequencies and value profiles, can be di#cult to collect using this approach. Current systems that collect this types of profiles via sampling Figure 1: Overview of instrumentation sampling framework [9] require relatively complex infrastructure as well as hardware support [4, 15, 41]. 2.3 Instrumentation Sampling To remove many of the existing limitations of instrumenting code online, we use the full duplication instrumentation sampling framework [9] a fully automatic compiler transformation that transparently reduces the overhead of executing instrumented code with ....

S. Subramanya Sastry, Rastislav Bodik, and James E. Smith. Rapid profiling via stratified sampling. In 28th International Symposium on Computer Architecture, 2001.

....many types of fine grained profiling information, such as basic block frequencies and value profiles, can be di#cult to collect using this approach. Current systems that collect these types of profiles via sampling require relatively complex infrastructure as well as hardware support [6, 24, 69]. 5.2 Design This section describes our design of an online FDO system that tries to improve upon the weaknesses of the previous approaches. Our online feedback directed approach assumes an execution environment in which a lightweight mechanism is used to identify hot methods and promote them to ....

....advantage that it amortizes the overhead of each check over multiple instrumentation operations (whereas the above techniques include one check per instrumentation operation) thus the Full Duplication framework reduces profiling overhead when instrumentation is not being performed. Sastry et al. [69] propose new hardware support for reducing profiling overhead. In their approach, profiling events are collected and compressed in hardware before being fed to a software profiler. Their simulation shows accuracy and overhead results similar to that of our Full Duplication sampling framework for a ....

S.Subramanya Sastry, Rastislav Bodik, and James E. Smith. Rapid profiling via stratified sampling. In 28th International Symposium on Computer Architecture, 2001.

....context tree [3] Burrows et al. 14] uses sampling to reduce the cost of profiling program values. These techniques are specialized examples of the general technique proposed by our framework, that is, using sampling to reduce the overhead of a previously exhaustive instrumentation. Recent work [34] proposes new hardware support for reducing profiling overhead. In their approach, profiling events are collected and compressed in hardware before being fed to a software profiler. Their simulation shows accuracy and overhead results similar to that of our work for a variety of profiling types, ....

S. Sastry, R. Bodik, and J. E. Smith. Rapid profiling via stratified sampling. In To appear in Sth International Symposium on Computer Architecture, 2001.

.... systems, software alone is used to gather program behavior information, either statically through binary instrumentation tools [18] or dynamically through just intime compilation [10] Recently an area of active research has been the architectural support of generating profiles at runtime [15, 8, 11, 12, 5]. These prior techniques, while very e#ective at assisting software based profiling, are dependent on the system software for management or the aggregation of events. We present a hardware only profiler that requires no support or knowledge of the overlying software layers. This will allow the ....

....instruction PCs, load addresses, register values, register names, cache misses etc. To profile a given event we need to combine multiple variables into an identification (or name) that uniquely represents that event. In this paper, motivated by the work by Sastry et al. on Stratified Sampling [15], we concentrate on profiling events that require a combination of only two types of information. We define a tuple to be a pair of values. This pair of values uniquely identifies the event that is going to be given as input to the profiler. An example tuple used for load value profiling could ....

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S. Sastry, R. Bodik, and J.E. Smith. Rapid profiling via stratified sampling. In 28th Annual International Symposium on Computer Architecture, June 2001.

....6.1 Low overhead Profilers One way to reduce the overhead of profiling is to do most of the work in hardware, possibly in parallel to the main computation. Techniques range from configurable performance counters that can trigger software interrupts [3, 12] over selection and compression [19] to programmable co processors [15, 23] Hardware profilers are typically instruction oriented: they count instructions with certain characteristics. The more sophisticated the hardware profiler, the less work remains to be done in software, so that a wide variety of profiling tasks can be done ....

....It is safe for profile compression to lose information, but the results must be a summary of the original data that allows immediate and fast extraction of the relevant information. Compression techniques that fit this bill range from counting, hashing, and other hardware preprocessing (e.g. [19]) to induction of hierarchical grammars [17] Finally, a common way to reduce the overhead of profiling is sampling. Hardware sampling is typically counterbased. In DCPI and ProfileMe, a sample is taken via an interrupt when one of the hardware performance counters of the Alpha processor ....

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S. Subramanya Sastry, Ratislav Bodk, and James Smith. Rapid profiling via stratified sampling. In International Symposium on Computer Architecture (ISCA), 2001.

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S. S. Sastry, R. Bodik, and J. E. Smith. Rapid Profiling via Stratified Sampling. In Proceedings of the 28th Annual International Symposium on Computer Architecture (ISCA-01), volume 29,3 of Computer Architecture News, pages 278--289, New York, June 2001. ACM Press.

....(2) a store profile, i.e. the set of memory addresses that were written in the profiled interval. Thanks to recent advances in sampling based profiling, these profiles can be collected with high accuracy, yet with overheads that are sufficiently low for dynamic optimizers (well below 5 slowdown) [3, 10, 15, 25, 26, 30]. We turn a constant propagator into a specializer by letting it consult the two profiles, essentially as follows: given a program point and an object that is frequently referenced at point , we perform standard constant propagation starting from , with two modifications: 1) we assume ....

....query and dotproduct are microbenchmarks used in the DyC project that we converted to Java. 7.3 Evaluating the store profile We first consider the overhead of our two profiles. In our infrastructure, we used a (simulated) hardware based stratified sampling scheme proposed by Sastry et al. [25]. Of course, one could use other software sampling based profiling schemes, such as that proposed by Arnold at al [3] The runtime overheads of these schemes are under 5 . We do not evaluate these overheads here, and instead refer to these studies. Regarding the memory requirements of the two ....

S. Subramanya Sastry, Rastislav Bodik, and James E. Smith. Rapid profilingvia stratifiedsampling. In Proceedings of the 28th Annual International Symposium on Computer Architecture (ISCA-01), volume 29,3 of Computer Architecture News, pages 278--289, New York, June 2001. ACM Press.

No context found.

S. Sastry, R. Bodk, and J. Smith. Rapid Profiling via Stratified Sampling. In Annual International Symposium on Computer Architecture, pages 278--289, July 2001.

No context found.

S. Subramanya Sastry, Rastislav Bodik, and James E. Smith. Rapid profiling via stratified sampling. In Proceedings of 28th Annual International Symposium on Computer Architecture, pages 278--289, July 2001.

No context found.

S. S. Sastry, R. Bodik, and J. Smith, "Rapid profiling via stratified sampling," in 28th Annual International Symposium on Computer Architecture, July 2001, pp. 278--289.

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