Batcher, K. E. The flip network of STARAN. In Proceedings International Conference on Parallel Processing (1976), pp. 65--71.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... to a large class of interconnection networks [22] In this paper, however, it will be discussed in the context of Multistage Interconnection Networks (MINs) Multistage Interconnection Networks (MINs) as reconfigurable networks have been studied extensively for multiprocessing applications [2, 8, 13, 20, 30, 32, 36]. A MIN connects a set of input ports to a set of output ports through multiple stages of interconnected switches. A path from an input port to an output port can be established through proper switch settings. In multiprocessing environments, a MIN is used to connect processors to either memory ....

....and Section 6 concludes the paper. 2. TIME DIVISION MULTIPLEXED MINs (TDM MINs) MINs under consideration in this paper are generalized cube networks [30] which are topologically equivalent to many blocking MINs such as Data Manipulator, flip, n cube, Omega, shuffle exchange and baseline [2, 8, 13, 20, 32, 36]. Figure 1 (a) shows an example of a 88 MIN with the generalized cube topology consisting of 22 switches. A 1616 MIN can be constructed recursively from two 88 MINs and an extra front stage, as shown in Figure 1 (b) In general, an N N MIN with the generalized cube topology can be constructed ....

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K.E. Batcher, "The flip network in STARAN," 1976 International Conference on Parallel Processing, pp. 65-71.

....notation. z This work was supported in part by DARPA, order number 7899, monitored by NIST under grant number 60NANB1D1150 and Ohio State University Seed Grant, No. 221337. 1 A large number of multistage interconnection networks have been proposed and implemented in multiprocessor systems [2, 3, 4, 9, 10, 19, 20, 22, 24, 27, 28, 29, 30]. These multistage interconnection networks typically connect a set of N processing elements to a set of N memory modules and perform various permutations among the two sets . The processing elements and memory modules are represented as N input and N output terminals. The permutations are ....

K. E. Batcher. The flip network in STARAN. In International Conference on Parallel Processing, pages 65--71, 1976.

....and vice versa when it is transferred between the two systems. This is referred to as either corner turning, data transposing, or format conversion. Typically, data is transposed using multidimensional access memory (MDA) and a flip or shuffle network like the ones used in STARAN [46] [47], or the MIT image processor [14] These methods require a lot of hardware, especially if the system is general purpose and its operands are not fixed to a particular size (bits) For example, even for such an application specific processor as the MIT pixelparallel image processing system [14] ....

Kenneth E. Batcher, "The Flip Network in STARAN", IEEE Transactions on Computers, February, 1977, pp 65-71.

....made of 2 Theta 2 switching elements is topologically equivalent to a class of blocking Multistage Interconnection Networks (MINs) including, for example, the Omega and the Baseline networks. Two control modes exist in such a MIN. One is individual switch control and the other is stage control [1]. The latter means that all the switching elements at the same stage are set to the same state, e.g. straight or cross. Hence, a single control bit (e.g. 0] for straight or [1] for cross) can be used to control all the switching elements at one stage. As a result, the size of a control word can ....

....Baseline networks. Two control modes exist in such a MIN. One is individual switch control and the other is stage control [1] The latter means that all the switching elements at the same stage are set to the same state, e.g. straight or cross. Hence, a single control bit (e.g. 0] for straight or [1] for cross) can be used to control all the switching elements at one stage. As a result, the size of a control word can be significantly reduced when compared to that required under individual switch control. In a Banyan, each input to output connection can be established along only one path ....

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K.E. Batcher, "The flip network in STARAN", Proceedings of International Conference on Parallel Processing, pp.65-71, 1976

....networks for parallel processing (see, for example, 4] 6] 15] 17] Nevertheless, there seems to be a surprisingly small number of basic designs for interconnection networks that recur under many disguises. A particularly ubiquitous geometry is the multistage shuffle exchange network [1], 5] 7] 11] 12] 14] 16] 19] This geometry provides good performance and simple message routing (or control) Given the paucity of other network geometries, one is tempted to conjecture that these networks are in some sense optimal. In this paper, we characterize the networks with simple ....

....of the baseline network [19] It is illustrated in Figure 9a for nodes with indegree and outdegree two. There are five other (fully labeled) networks that are known to be isomorphic to baseline networks. These are the reverse baseline networks [19] the omega networks [11] the flip networks [1], the modified data manipulators [5] and the indirect binary cube networks [14] See [12] 16] or [19] for a proof of their isomorphism. It turns out that these networks are obtained by slightly varying the naming scheme that yields the baseline network: the two address parts may be ....

K. E. BATCHER, The Flip Network in STARAN, Proc. 1976 Int. Conf. Parallel Processing, 65-71. Ultracomputer Note 106

....5] such that a is less than 4, negate a . The expression returns [ 3, 4, 9] Parallelism is available both in the evaluation of the expression to the left of the colon ( and in the subselection to the right of the pipe ( This parallel subselection can be implemented with packing techniques [6]. NESL also supplies a set of parallel functions that operate on sequences as a whole. Figure 2 lists several of these functions; a full list can be found in the NESL manual [11] These are similar to operations found in other data parallel languages. NESL supports nested parallelism by allowing ....

....Figure 6: The main tasks of the NESL compiler. nested operations into segmented 1 VCODE operations on the flattened representation. The flattening of nested sequences is achieved by converting each sequence into a pair: a value vector and a set of segment descriptors. For example, the sequence [2, 9, 1, 5, 6, 3, 8] would be represented by the pair segdes = 7] value = 2, 9, 1, 5, 6, 3, 8] and the nested sequence [ 2, 1] 7, 0, 3] 4] would be represented as segdes1 = 3] segdes2 = 2, 3, 1] value = 2, 1, 7, 0, 3, 4] In these examples, a segdes with only one value specifies that the whole vector is ....

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Kenneth E. Batcher. The flip network of STARAN. In Proceedings International Conference on Parallel Processing, pages 65--71, 1976.

....networks. 2 Preliminaries 2. 1 k ary n cubes Many different network topologies have been proposed for use in concurrent computers: trees [6] 15] 21] Benes networks[4] Batcher sorting networks [2] shuffle exchange networks [23] Omega networks [14] indirect binary n cube or flip networks [3] [22] and direct binary n cubes Figure 1: A Binary 6 Cube Embedded in the Plane [19] 17] 24] The binary n cube is a special case of the family of k ary n cubes, cubes with n dimensions and k nodes in each dimension. Most concurrent computers have been built using networks that are either ....

Batcher, K.E., "The Flip Network in STARAN," Proceedings, 1976 International Conference on Parallel Processing, pp. 65-71.

....to apply functions in parallel to each element of a sequence. The application of a function over a sequence is specified using a set like notation similar to set formers in Setl [37] and list comprehensions in Miranda [44] and Haskell [26] For example, the Nesl expression negate(a) a in [3, 4, 9,5] a 4 can be read as in parallel, for each a in the sequence [3, 4, 9, 5] such that a is less than 4, negate a . The expression returns [ 3, 4, 9] The parallelism is applied both to the expression to the left of the colon ( and to the subselection to the right of the pipe ( This ....

.... of a function over a sequence is specified using a set like notation similar to set formers in Setl [37] and list comprehensions in Miranda [44] and Haskell [26] For example, the Nesl expression negate(a) a in [3, 4, 9,5] a 4 can be read as in parallel, for each a in the sequence [3, 4, 9, 5] such that a is less than 4, negate a . The expression returns [ 3, 4, 9] The parallelism is applied both to the expression to the left of the colon ( and to the subselection to the right of the pipe ( This parallel subselection can be implemented with packing techniques [5] Nesl also ....

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K. E. Batcher. The flip network of STARAN. In Proceedings International Conference on Parallel Processing, pages 65--71, 1976. 2 A full implementation of NESL is available from blelloch@cs.cmu.edu.

....like the first stage while the cyclic edges at each stage appear as the unshuffle connection pattern [1, 7, 9] Fig. 5(c) can be contracted to Fig. 5(e) by squeezing every pair of nodes into one big node shown in Fig. 5(d) Fig. 5(e) is apparently a reverse Omega network (or a flip network [3]) Hence the original CCC n is turned into a reverse Omega network with 1 2 n inputs and 1 2 n outputs. Note that the reverse Omega network (with 1 2 n inputs and 1 2 n outputs) has the banyan property [10] each input node u is connected to each output node v by exactly one path of length ....

K. E. Batcher. The flip network in STARAN. In Proceedings of International Conference on Parallel Processing, pages 65--71, Detroit, MI, 1976.

....of the switches in the path. In this paper, the n stages of a delta network are numbered from 0 to n 0 1 (the inputs connect to stage 0) The switches in each stage are numbered from 0 to b n01 0 1. There are many MIN s in this class, including the baseline [23] SW banyan [8] omega [12] ip [3], and indirect binary n cube [18] networks. They are topologically equivalent [2, 15, 23] so the choice between them is mainly a matter of which one is easiest to implement in a particular system. The important property they all have in common is that from any input port in stage 1 This was ....

K. E. Batcher. The Flip Network in STARAN. In Proceedings of the 1976 International Conference on Parallel Processing, pages 65--71, Detroit, Michigan, August 1976.

....together like the first stage while the cycle edges at each stage appear to be in the unshuffle connection pattern [1, 8] Fig. 6(c) can be transformed into Fig. 6(e) by replacing every pair of nodes with a complex node as shown in Fig. 6(d) Fig. 6(e) is a reverse Omega network (or a flip network [3]) Hence, the original CCC(n) is transformed into a reverse Omega network with 1 2 n inputs and 1 2 n outputs. Note that the reverse Omega network (with 1 2 n inputs and 1 2 n outputs) has the banyan property [10] each input node u is connected to each output node v by exactly one path of ....

K.E. Batcher. The flip network in STARAN. In Proc. International Conference on Parallel Processing, pages 65--71, Detroit, MI, 1976.

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Batcher, K. E. The flip network of STARAN. In Proceedings International Conference on Parallel Processing (1976), pp. 65--71.

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K.E.Batcher, The Flip Network in STARAN, Proc. 1976, Int. Conference Parallel Processing, 65-71

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