C.-H. Yeh, B. Parhami, E. A. Varvarigos, and H. Lee, "VLSI layout and packaging of butterfly networks," in Proc. of the 12th ACM Symp. on Parallel Algorithms and Architectures (SPAA), July 2000, pp. 196--205. Home/Search Document Details and Download
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On-Chip Interconnects for Next Generation System-on-Chips - Brinkmann, Niemann.. (2002) (Correct)
....that some metal layers of the fabrication process are dedicated to the wiring between the switch boxes. Efficient layout patterns have been developed which are able to minimize the required layer consumption and support different interconnection topologies, like meshes or butterfly networks [8] [9]. The parallel structure of the switch box architecture offers a high potential for fault tolerance. In case of a failure of one or more components other parts of the SoC can take over the respective operations. This may cause a strong increase of production yield. Furthermore, the topology is ....
C.-H. Yeh, B. Parhami, E. A. Varvarigos, and H. Lee, "VLSI layout and packaging of butterfly networks," in Proc. of the 12th ACM Symp. on Parallel Algorithms and Architectures (SPAA), July 2000, pp. 196--205.
Parallel Algorithms for Index-Permutation Graphs - An.. - Yeh, Parhami Self-citation (Yeh Parhami) (Correct)
....a constant number of off chip links, each of which has bandwidth Q(w) so the bisection bandwidth is Q i wN logN j , which is of the same order as that of a similar size hypercube. The bisection width of an N node butterfl y is Q i N logN j . By using the partitioning that we proposed in [32], the intercluster degree of a butterfl y node is only Q i log M N logN j . Therefore, the bisection bandwidth of the butterfl y network is Q i wN log M N j , which is higher than that of a similar size hypercube. 2 When M = N e , where e is a constant smaller than 1, we have l = log ....
Yeh, C.-H., B. Parhami, E.A. Varvarigos, and H. Lee, " VLSI layout and packaging of butterfl y networks," Proc. ACM Symp. Parallel Algorithms and Architectures,
On the VLSI Area and Bisection Width of Star Graphs and.. - Yeh, Parhami Self-citation (Yeh Parhami) (Correct)
....of their node addresses modulo i are the same, and each of the m Gamma i type i links is placed in a different track if i m=2, It can be seen that such an arrangement will not result in overlapped links within a track. More details concerning the collinear layout of complete graphs found in [27, 31]. The total number of tracks in the layout described above is equal to m Gamma1 i=1 min(i;m Gamma i) bm=2c i=1 i m Gamma1 i=bm=2c 1 (m Gamma i) bm=2c i=1 i dm=2e Gamma1 i=1 i = bm 2 =4c: Since the bisection width of Km is equal to m 2 =4 when m is even and (m 2 ....
....than the one given in [22] by a factor of 72 and is optimal within a factor of 1 o(1) as will be seen from the lower bound derived in Section 3. Similar results can be obtained for pancake graphs and bubble sort graphs [3] 2.4. Multilayer layout for star graphs In the multilayer 2 D grid model [31, 30], a network is viewed as a graph whose nodes correspond to processing elements and edges correspond to communication links. The nodes and edges of the graph are then embedded in a 3 D grid, where edges have unit width, can run along grid lines, but cannot cross or overlap with each other (i.e. ....
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Yeh, C.-H., B. Parhami, E.A. Varvarigos, and H. Lee, " VLSI layout and packaging of butterfl y networks," Proc. ACM Symp. Parallel Algorithms and Architectures,
Multilayer VLSI Layout for Interconnection Networks - Yeh, Varvarigos, Parhami (2000) Self-citation (Yeh Parhami Varvarigos) (Correct)
....The layout of interconnection networks has important cost and performance implications for single chip multiprocessors and parallel distributed systems based on such components. Thus, there is currently renewed interest in fi nding effi cient VLSI layouts for various interconnection networks [3, 8, 10, 12, 13, 21, 28, 30, 31, 32, 35]. VLSI layout of interconnection networks is usually derived under the Thompson model, where two layers of wires are assumed. However, the assumption of two wiring layers cease to be realistic as more and more layers of wires become available in VLSI chips at reasonable cost. When the numbers of ....
.... hypercubes, butterfl y networks, cube connected cycles (CCC) 22, 18] folded hypercubes [1] generalized hypercubes [5, 14] k ary n cube cluster c [4] hierarchical hypercube networks (HHNs) 36] reduced hypercubes [37] hierarchical swap networks (HSNs) 33, 34] indirect swap networks (ISNs) [35], designing layouts under the multilayer 2 D grid model leads to the following advantages: 1) the area of the layout can be reduced by a factor of approximately t 2 when we use L = 2t layers of wires instead of two layers of wires as in the Thompson model (2) the volume of the layout can be ....
[Article contains additional citation context not shown here]
Yeh, C.-H., B. Parhami, E.A. Varvarigos, and H. Lee, " VLSI layout and packaging of butterfl y networks," Proc. ACM Symp. Parallel Algorithms and Architectures, 2000, to appear.
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