C.R. Ho, "Validation Tools for Complex Digital Designs", Ph.D. Thesis, Stanford University, Dec. 1996. Home/Search Document Details and Download
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Assertion Checking by Combined Word-level ATPG and Modular.. - Huang, Cheng (2000) (3 citations) (Correct)
....each of the comparator inputs. For example, suppose a 4 bit greater ( gate has output value 1 (TRUE) and input values in a = 4 bx01x and in b = 4 b1x0x (Fig. 4) By setting all the x s to 0 s and then to 1 s, we learn that in a has the minimum and maximum values [min a, max a] equal to [2, 11], and in b has [min b, max b] 8, 13] However, for the greater gate to be evaluated TRUE , it implies min a must be greater than min b , and max b must be smaller than max a . Adjusting the values of min a and max b , we have [min a, max a] 9, 11] and [min b, max b] 8, 10] ....
C.R. Ho, "Validation Tools for Complex Digital Designs", Ph.D. Thesis, Stanford University, Dec. 1996.
Functional Design Verification For Microprocessors By Error.. - Van Campenhout (1999) (Correct)
....are usually restricted in length. An advantage of self checking tests is that only the implementation needs to be simulated. The absence of a suitable simulatable reference model (specification) makes it the only choice for correctness checking. The use of self checking tests has been reported in [Chan94, Ho96a]. Kantrowitz and Noack [Kant96] worked on the functional verification of a commercial superscalar microprocessor. They reported some of these difficulties associated with self checking tests, and mainly used the co simulation approach to correctness checking. Co simulation. The second approach ....
....and mainly used the co simulation approach to correctness checking. Co simulation. The second approach for automated checking is to simulate the implementation and the specification together and to compare the states of both machine constantly. This approach has been referred to as co simulation [Ho96a]. A discrepancy between implementation and specification states indicates either an error in the implementation (a design error) or an error in the reference model. Provided that the reference model and the implementation are developed independently, it is very unlikely that both models exhibit ....
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C.-M. R. Ho. Validation tools for complex digital designs. PhD thesis, Stanford University, 1996.
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