J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Modulo scheduling with integrated register spilling for clustered VLIW architectures. In Proceedings of the 34th Annual International Symposium on Microarchitecture, pages 160-- 169, Austin, Texas, Dec. 2001.  Home/Search Document Details and Download
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This paper is cited in the following contexts:
Exploiting Pseudo-schedules to Guide Data.. - Aleta, Codina.. (2002) (2 citations) (Correct)
....a framework to deal with instruction scheduling, cluster assignment and register allocation in a single phase, including a unique approach to insert spill code onthe fly and provides effective mechanisms to deal with communications, register and memory pressure at the same time. Zalamea et al. [38] also proposed a technique to cluster assignment, instruction scheduling and register allocation based on an iterative scheme [32] with some heuristics to deal with spill code on the fly [37] Aleta et al. 1] presented a graph partitioning based approach with close interaction to the ....
J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures. In Proc. of the 34th Int. Symp. on Microarchitecture, December 2001.
Convergent Scheduling: A Flexibla and Extensible Scheduling.. - Puppin (2002) (Correct)
....combined approach to perform scheduling and partitioning on a VLIW DSP [Leu00] The approach is based on simulated annealing. Integrated approaches to partitioning, scheduling and register allocation can also be found in the area of modulo scheduling for clustered VLIW architectures [SG00, 73 ZLAV01] However, there have been far fewer space time scheduling algorithms that take into account preplaced instructions. One such algorithm is BUG (Bottom Up Greedy) BUG is implemented on ELI, one of the earliest spatial architectures that relies on the compiler for space time scheduling [Ell85] ....
Javier Zalamea, Josep Llosa, Eduard Ayguade, and Mateo Valero. Modulo scheduling with integrated register spilling for clustered vliw architectures. In MICRO34, 2001. 84
AND COMPILER MANAGEMENT OF ORGANIZATION AND COMPILER.. - Of The Requirements Self-citation (Zalamea Llosa Ayguade) (Correct)
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J. Zalamea, J. Llosa, E. Ayguade, and Mateo Valero. Modulo scheduling with integrated register spilling for clustered VLIW architectures. In (MICRO--34), pages 160--169, December 2001.
Software and Hardware Techniques to Optimize.. - Zalamea, Llosa.. (2001) (4 citations) Self-citation (Zalamea Llosa Ayguad'e Valero) (Correct)
....In this subsection we explain the additional actions (steps C1 and C2 in the algorithm shown in Figure 14) and modifications required when compiling for clustered architectures. These actions imply cluster selection, insertion, scheduling and ejection of move operations. The reader is referred to [47] for additional details about MIRS C. A.1 Cluster selection After picking up the u node in (step 2) the algorithm decides the most appropriate cluster (i) to schedule it (step C1) This is done taking into consideration (in the specified order) the following aspects: ffl Availability of empty ....
....shown in Figure 3, configuration with k=4 (k=2) reduces the area by a factor of 0.15 (0.36) and power consumption by a factor of 0.49 (0. 67) For a broader evaluation of clustered architectures using real memory and applying binding prefetching to hide the negative effect of misses is included in [47]. V. Conclusions High performance microprocessors are currently designed to exploit the inherent ILP available in most applications. The techniques used in their design and the aggressive scheduling techniques tend to increase the register requirements of the loops. In this paper we have done an ....
J. Zalamea, J. Llosa, E. Ayguad'e, and M. Valero, "Modulo scheduling with integrated register spilling for clustered vliw architectures," Tech. Rep. UPC-DAC-
Optimizing Loop Performance for Clustered VLIW Architectures - Qian, Carr, Sweany (2002) (2 citations) (Correct)
No context found.
J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Modulo scheduling with integrated register spilling for clustered VLIW architectures. In Proceedings of the 34th Annual International Symposium on Microarchitecture, pages 160-- 169, Austin, Texas, Dec. 2001.
Exploiting Pseudo-schedules to Guide Data.. - Aleta, Codina.. (2002) (2 citations) (Correct)
No context found.
J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures. In Proc. of the 34th Int. Symp. on Microarchitecture, December 2001.
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