M. C. Herbordt. The Evaluation of Massively Parallel Array Architectures.PhD thesis, University of Mass., Departmentof ComputerScience, 1994. also TR9507.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....2 32 bit words are available, the machine will perform a large number of memory spills. With the growing gap between processor and memory speeds, this effect becomes critical. 2.4. 2 Simulation Based Performance Evaluation A simulation approach to SIMD performance evaluation was taken by Herbordt (Herbordt 1994). His trace compilation technique compiled traces generated on an abstract virtual machine for a specific target architecture. The technique can be two orders of magnitude faster than a detailed simulation. This flexibility allows quick evaluations of different architectural parameters, such as ....

....by floating point manipulations. Program f A Bitonic Sort 0.75 Matrix Product 0.94 LU Decomposition 0.76 Cholesky Decomposition 0.25 Jacobi Method 0.91 SOR Method 0.91 SIMPLE 0.71 Table 6.2: Fraction of Operation Costs Affected by Data Path Width. From (Holman Snyder 1989) Herbordt s (Herbordt 1994) evaluation of parallel architectures included a set of simulation results relating datapath width to execution time. The value of f A was extracted by fitting Amdahl s function to the published performance curves. The fitted functions agreed well with the simulation data, although half of the ....

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Herbordt, M. C. (1994), The Evaluation of Massively Parallel Array Architectures, PhD thesis, University of Massachusetts at Amherst.

....allowing an agent to control its computation depending on its duration. Simulation modeling is also important when evaluating novel computer architectures, such as new cache architectures or special parallel hardware for signal processing or computer vision. Martin Herbordt s dissertation [26] gives an excellent survey of techniques for simulating and evaluating computer architectures. The main idea is to devise a representative workload in terms of programs to run on the new hardware, execute the programs (in some way) to get a long trace of the assembly language instructions they ....

Herbordt, M. C. The Evaluation of Massively Parallel Array Architectures. PhD thesis, University of Massachusetts at Amherst, 1994.

....example shown in detail is of a systolic type. Short computation DRAFT VERSION OF September 26, 1995 8 chains between virtual PE synchronizations could lead to a large number of register save and restore operations. A simulation approach to SIMD performance evaluation was taken by Herbordt [15]. Traces are generated on an abstract virtual machine and then trace compiled for a specific target architecture. The technique can be two orders of magnitude faster than a detailed simulation. This flexibility allows quick evaluations of different architectural parameters, such as register file ....

M. C. Herbordt, The Evaluation of Massively Parallel Array Architectures. PhD thesis, University of Massachusetts at Amherst, 1994.

....at least as powerful as a nearest neighbor mesh. Feedback from array to controller is provided by a global OR circuit. We partition the optional part of the architectural design space into features and parameters. The distinction was inspired by Snyder s work [18] and is defined formally in [9]. Roughly speaking, a parameter is a component for which a reasonable compiler could be expected to make algorithmic decisions without user input; the opposite is true of features. In general, all components of serial processors are parameters. These include the number of registers, the width of ....

M.C. Herbordt (1992): "The Evaluation of Massively Parallel Array Architectures," Technical Report, Department of Computer Science, University of Massachusetts.

....We have found that the virtual machine emulation of typical image understanding applications takes from a few seconds to a few minutes and from 30 to 487 times faster than on the CAAPP instruction level simulator. A sample of these results is shown in Table 6. The applications are described in [14]. The time needed to generate a complete set of 18 app. elapsed time speedup platfm caapp sim. vm emul. IU Benchmark 1:41:20 0:03:20 30.5 1 (64x64) FP Convolve 1:51:33 0:01:38 68.3 1 IU Benchmark 9:19:08 0:13:58 69.0 2 (256x256) Matcher 0:49:03 0:00:20 147.2 2 Prewitt 1:45:31 0:00:13 ....

Herbordt, M. C. The Evaluation of Massively Parallel Array Architectures. PhD thesis, Dept. of Comp. Sci., U. of Mass. (also TR95-07), 1994.

....benchmarks such as SPEC [26] are not appropriate. Rather, we have taken the approach of evaluating MPAs with respect to representative sets of programs within the domains where they are to be used. One such domain is spatially mapped computer vision applications; they are described in detail in [8]. Some general comments are as follows: they are all non trivial in that they consist of from several hundred to several thousand lines of code; they are, with the exception of the IU Benchmark, in use in a research environment; and they span a wide variety of types of computations. As an example ....

....results. 6.4 Performance We have found that applications run from 24 to 487 times faster on the virtual machine emulator than on the CAAPP instruction level simulator. Speedups of between 60 and 70 are the norm. A sample of these results is shown in Table 2. The applications are described in [8]. Virtual machine emulation is efficient even when compared with running native workstation code. In cases where there are serial, non ICL, versions of application codes, we have found their execution times comparable to their ICL counterparts (i.e. within 20 and sometimes virtually identical) ....

Herbordt, M. C. The Evaluation of Massively Parallel Array Architectures. PhD thesis, Dept. of Comp. Sci., U. of Mass. (also TR95-07), 1994.

....applications including region and line segmentation, line finding through perceptual organization, hough transforms, graph matching, extraction of structure from motion, and in solving many problems from computational geometry. For a sample of this work see [31, 25, 28, 18] and the references in [14]. Even so, SIMD designs have never converged to a particular set of attributes, at least not nearly to the same extent as have serial computers or even shared memory multiprocessors. Many fundamental design questions including granularity, datapath design, memory hierarchy, and, especially, ....

Herbordt, M. C. The Evaluation of Massively Parallel Array Architectures. PhD thesis, Dept. of Comp. Sci., U. of Mass. (also TR95-07), 1994.

....with the exception of the IU Benchmark, in use in a research environment; and they span a wide variety of types of computations. As an example of the last point, some are dominated by gray scale computation (which is mostly 8 bit integer) others by floating point. They are described in detail in [3]. 2.3 Mapping Applications to Architectures: Virtual PEs The standard MPA programmer s model maps elements of parallel variables to individual PEs. It is rarely the case, however, that a processor has enough PEs to create this precise mapping; rather, some number of elements must be mapped to ....

Herbordt, M. C. The Evaluation of Massively Parallel Array Architectures. PhD thesis, Dept. of Comp. Sci., U. of Mass. (also TR95-07), 1994.

....to be solved in time to be useful to the end user, if they can be solved at all. Although determining the kind (or kinds) of massive parallelism best applied to each particular problem continues to be a research issue [9] SIMD arrays remain a leading candidate for many of these computations [13, 18, 5]. The problem this work addresses is the allocation of resources within and among architectural components for future generation SIMD arrays in light of increased VLSI process and packaging capabilities. Although SIMD arrays are somewhat less popular now than they were, say, before 1992, they ....

....and inter PE router network. Also explored are PE cache design parameters such as size, replacement algorithm, block size, and associativity. The system used to perform these simulations is ENPASSANT (ENvironment for PArallel System Simulation ANalysis Tools) which is described in detail in [5]. The most significant results are as follows: ffl The shapes of the memory reference time versus register file size curves indicate distinct reference locality. This is significant as SIMD arrays are still being built with flat memory hierarchies. ffl Adding another level to the PE memory ....

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Herbordt, M. C. The Evaluation of Massively Parallel Array Architectures. PhD thesis, Dept. of CS, U. of Mass. (also TR95-07), 1994.

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M. C. Herbordt. The Evaluation of Massively Parallel Array Architectures.PhD thesis, University of Mass., Departmentof ComputerScience, 1994. also TR9507.

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