J. Zalamea, J. Llosa, E. Ayguade, M. Valero, Two-level Hierarchical Register File Organization for VLIW Processors, IEEE Symposium on MICRO, pp-137-146, 2000;  Home/Search   Document Details and Download   Summary   Related Articles   Check

....However, the penalty is a potentially larger size and access time for the L1. Hence, the choice of which organization works better would depend on the target frequency, the process parameters (the register file size that can be supported in a single cycle) and the benchmark set. Zalamea et al. [31] proposed a two level register file that is compiler controlled for reduced register spilling in the context of VLIW processors. The Cray 1 [23] also implemented a software controlled two level hierarchical register file. Yung and Wilhelm [30] explored the possibility of caching part of the ....

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Two-Level Hierarchical Register File Organization for VLIW Processors. In Proceedings of MICRO-33, Dec 2000.

....these resources. Lebeck et al. 10] propose a two level hierarchical instruction window to keep the effective sizes large and yet the primary structure small and fast. The buffering of the state of all the in flight instructions is achieved through the use of two level register files similar to [3, 24], and a large load store queue. Instead, we focus on improving the effective size of resources while keeping their actual sizes small. We believe that these two techniques are complementary, and could have an additive effect. Finally, we notice that, concurrently to our work, Cristal et al. 2] ....

J. Zalamea, J. Llosa, E. Ayguad e, and M. Valero. Two-level hierarchical register file organization for VLIW processors. In International Symposium on Microarchitecture, pages 137--146, Monterey, CA, December 2000.

....yet not fully consistent register files [21] Cruz et al. proposed a multiple bank register file [22] for dynamically scheduled processors in which the architected registers are assigned at run time to multiple register banks. Zalamea et al. have proposed a two level hierarchical register file [23] explicitly managed using two new spill instructions. In contrast, CRB is transparent to the register allocator; it is not assigned any architected name space, which in turn allows it to cache any architected register. Due to space limitations, readers are referred to [8] for a more comprehensive ....

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero, "Two-level hierarchical register file organization for VLIW processors," in Proceedings of the 33rd Annual International Symposium on Microarchitecture (MICRO-33), 2000.

....the rst level proposed by Cruz et al., possibly implying a longer cycle time. Hence, the choice of which organization works better would depend on the target frequency, the process parameters (the register le size that can be supported in a single cycle) and the benchmark set. Zalamea et al. [24] also proposed a two level hierarchical register le in the context of VLIW processors. The level 1 and level 2 registers are both visible to the compiler and it explicitly manages the transfer of values between the two levels. The improvement in performance comes about because of the reduced ....

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Two-Level Hierarchical Register File Organization for VLIW Processors. In Proceedings of MICRO-33, Dec 2000. 20

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J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Two-level hierarchical register file organization for vliw processors. In Proceedings of the 33rd International Symposium on Microarchitecture (MICRO--33)), pages 137-- 146, December 2000.

....Reference [37] proposes a caching mechanism for the register file in dynamically scheduled processors. The organization is hierarchical and the allocation of values to registers is performed at runtime. The mechanism is transparent to the compiler and acts as a cache for the register file. In [38] the authors propose a two level hierarchical register file organization, as shown in Figure 11.c. The first level, named R1, has a small capacity but a high number of ports (in order to feed all the functional units) this will permit a design with a small access time. The second level, named R2, ....

....operation. The compiler can also move data between levels in order to spill values when the pressure in R1 is higher than its capacity. The explicit management of these data movements requires modifications in the algorithm used for register allocation and spilling. The algorithm proposed in [38] first allocates registers in R1 using the wands only strategy with end fit and adjacency ordering [23] If there are not enough registers in R1, spill code between R1 and R2 is inserted. Spill code is added using the techniques proposed in [14] and using only the loadR and storeR instructions. ....

J. Zalamea, J. Llosa, E. Ayguad'e, and Mateo Valero, "Twolevel hierarchical register file organization for vliw processors, " in 33rd International Symposium on Microarchitecture (MICRO-33)), December 2000, pp. 137--146.

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J. Zalamea, J. Llosa, E. Ayguade, M. Valero, Two-level Hierarchical Register File Organization for VLIW Processors, IEEE Symposium on MICRO, pp-137-146, 2000;

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J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Two-level hierarchical register file organization for VLIW processors. In Proceedings of the 33rd International Symposium on Microarchitecture, pages 137--146, December 2000.

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J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Two-level Hierarchical Register File Organization for VLIW Processors. In International Symposium on Microarchitecture, pages 137--146, Monterey, California, December 2000.

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J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. TwoLevel Hierarchical Register File Organization For VLIW Processors. In Proceedings of the 33rd Annual International Symposium on Microarchitecture, pages 137--146, December 2000.

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J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Twolevel hierarchical register file organization for VLIW processors. In Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture (Micro-33), pages 137--146, Los Alamitos, CA, December 10--13 2000. IEEE Computer Society. 12

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J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Two-level hierarchical register file organization for VLIW processors. In Proceedings of the 33rd International Symposium on Microarchitecture, pages 137--146, December 2000.

No context found.

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Two-level hierarchical register file organization for VLIW processors. In International Symposium on Microarchitecture, 2000.

No context found.

J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Two-Level Hierarchical Register File Organization For VLIW Processors. In Proceedings of the 33rd Annual International Symposium on Microarchitecture, pages 137--146, December 2000.

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J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. TwoLevel Hierarchical Register File Organization For VLIW Processors. In Proceedings of the 33rd Annual International Symposium on Microarchitecture, pages 137--146, December 2000.

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