S. Lee and P. Yew. On some implementation issues for value prediction on wide-issue ILP processors. In International Conference on Parallel Architectures and Compilation Techniques, pages 145--156, Oct 2000.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....studies have shown that substantial performance gains may be made possible by predicting the data values that are likely to be produced by instructions [1 11] This value prediction breaks true data dependences to reveal previously unavailable instruction level parallelism. A few previous studies [3,5,8] have shown, however, that the speedups obtained by using value predictions with realistic updates may drop significantly compared to those obtained when using the unrealistic immediate update assumption. While the immediate update assumption allows subsequent predictions to use the actual, ....

.... that have not yet resolved for each entry of the value prediction table can provide at least a partial relationship between the most recently updated value to the entry and the value that should be predicted for the current instruction instance that is requesting a prediction from this entry [3,12]. For instance, Lee and Yew [3] proposed adding an age field in each entry of a stride predictor to record the number of outstanding instructions that requested a prediction with the entry since it was last updated with a known correct value. The value predictor then makes a prediction for the ....

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S. Lee and P. Yew. "On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors." International Conference on Parallel Architecture and Compiler Techniques (PACT2000.

.... this locality requires a significant investment in hardware for modest prediction accuracy [7, 18, 25, 30] But if the hardware cost can be tolerated and high accuracy can be reached, value prediction can reduce pipeline stalls by introducing more (speculatively) independent instructions [7, 16, 17, 18, 22, 23], introducing helper instructions such as prefetches [1] enhancing branch prediction [11] and enabling speculative multithreading [15, 19, 31] This paper introduces novel value prediction schemes that leverage a new kind of value locality based on global stride information. The resulting ....

....value locality, those experiments did not take any delay in value history into account. Due to pipeline delay, especially in out of order (OOO) execution pipelines, the correlated values may not be available when the prediction is being made. Although this issue exists for local value predictors [16, 22] (the local prediction results in Figure 16 confirm this problem) the impact for those predictors is small except for cases such as tight loop code, which calls for the speculative update based on the prediction (the importance of speculative updating branch history is observed earlier in [10] ....

S. Lee and P. Yew, "On some implementation issues for value prediction on wide ILP processors", in International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000.

....computes a new prediction. This predicted value is stored in a Prediction Value Cache (PVC) and can be used by the next instance of the instruction. Two versions of the decoupled value predictor have been presented, one for machines with trace caches [12] and one for machines with no trace cache [13]. The trace cache strategy is used in this paper since it fits perfectly within the wide issue environment being evaluated. The following summary applies to both strategies. The fill unit [26] stores the predicted value and some additional bits for each instruction in the PVC. This cache is ....

S. Lee and P. Yew. On some implementation issues for value prediction on wide-issue ILP processors. In Compilation Techniques, pages 145--156, Oct 2000.

....for the VP Tint and two versions of table based stride value predictors. The mean is presented as a geometric mean throughout the results unless noted. Stride prediction is done with a basic stride predictor [9] with 4096 entries. Although there are more complex methods of value prediction [18, 35, 40], we study a large stride predictor because it is more easily realizable and captures both the striding and last value behaviors. The 16 port stride predictor presented in the figure (Stride VP Port 16) can accommodate up to 16 predictions and updates each cycle. The second stride predictor ....

....ports. The precise reason is di#cult to isolate since performance benefits of value prediction are based on a combination of factors, such as misprediction rate, prediction confidence, update frequency, varying rewards for correct predictions, and varying penalties for mispredictions [18, 34]. Table 4: Analysis of Value Prediction E#ectiveness VP Tint MP Rate 7.57 7.84 4.03 8.89 5.37 5.55 17.51 SVP 2 MP Rate 13.00 13.57 5.21 16.26 8.41 8.26 29.27 VP Tint Coverage 98.43 84.20 94.64 95.98 95.56 99.93 99.71 SVP 2 Coverage 99.18 77.42 69.36 82.39 77.28 98.78 99.34 parser perlbmk ....

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S. Lee and P. Yew. On some implementation issues for value prediction on wide-issue ILP processors. In International Conference on Parallel Architectures and Compilation Techniques, pages 145--156, Oct 2000.

....computes a new prediction. This predicted value is stored in a Prediction Value Cache (PVC) and can be used by the next instance of the instruction. Two versions of the Decoupled value predictor have been presented, one for machines with trace caches [11] and one for machines with no trace cache [12]. The trace cache strategy is used in this paper since it first perfectly within the wide issue environment which we are studying. The following summary applies to both strategies. The fill unit [26] stores the predicted value and some additional bits for each instruction in the PVC. This cache ....

....value prediction from the critical path in instruction fetch and to reduce the port requirements for the four value prediction tables. The architecture provide update queues and allow two ports for updating the predictor. Lee and Yew also propose a similar system for use with an instruction cache [12]. Gabbay and Mendelson study the e#ects of fetch bandwidth on value prediction [9] The authors propose a highly interleaved prediction table for trace cache processors to address the observations and issues uncovered in their work. Their simulated architecture uses idealized components to stress ....

S. Lee and P. Yew. On some implementation issues for value prediction on wide-issue ILP processors. In International Conference on Parallel Architectures and Compilation Techniques, pages 145--156, Oct 2000.

....it has been updated. This 3 most likely will cause incorrect value predictions. In this paper, we address those implementation issues for wide issue architectures. We augment the instruction cache with a prediction value cache (PVC) to hold prediction values for each instruction in a cache block [4]. It not only allows multiple accesses to the prediction values in each machine cycle, but also allows us to move the value prediction from the instruction fetch stage to a later pipeline stage after the update values are produced. We assume each prediction table has only 2 read write ports with ....

....value update (which usually occurs in a later stage of the pipeline) and the prediction value usage (which usually occurs in an early stage of the pipeline) Therefore, 4 many instructions may access stale prediction values from the table before they can be actually updated. In our paper [4], we could see, on average, 36 of instructions access the same table entry again within 5 cycles and 22 of the instructions access the same table entry within 2 cycles. This effect can cause serious performance degradation because stale values mostly are incorrect, especially for stride and ....

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S.Lee, and P.Yew, "On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors", International Conference on Parallel Architectures and Compilation Techniques (PACT

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S. Lee and P. Yew. On some implementation issues for value prediction on wide-issue ILP processors. In International Conference on Parallel Architectures and Compilation Techniques, pages 145--156, Oct 2000.

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