T.G. Rokicki and C.J. Myers, Automatic Verification of Timed Circuits, Proc. CAV'94, June, 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....in [5] and consequently the efficiency of the verification process. We also show how the efficiency of verification can be further improved by combining the transformational and clustering approaches. Several analysis techniques based on time extensions of Petri nets have been proposed [15] [13], 16] 10] These approaches, though implementing efficient verification algorithms, are not totally suitable for real time embedded systems since their modeling formalisms do not capture important features of such systems, for instance data dependencies as expressed by guards in PRES . The ....

T. G. Rokicki and C. J. Myers, "Automatic Verification of Timed Circuits," in Computer-Aided Verification, D. L. Dill, Ed. LNCS 818, Berlin: Springer-Verlag, 1994, pp. 468-480.

.... #and # # such that w # #O j , M = y(w # ,# # )and latest(y, w # ,M j ) # latest(y, w,M k ) hold Cond6)# 6: There are no j, w #and # # such that j #= k, w # #O j , M = y(w # ,# # )and latest(y, w # ,M j ) # latest(y, w, M k )hold u (b) c) wu I= w O= u I= u O= w M 1 M 2 [4,6] [3,6] 2,7] w I= w O= M 1 [1,10] w I= O= w M 2 [1,20] u I= u O= M 1 [2,7] u I= O= u M 2 [4,5] a) Figure 4: Examples of mod,A sets. Intuitively a timing failure occurs when a mod6q expects an input but it will not be given in time. Here there are several interpretations on ....

.... 6: There are no j, w #and # # such that j #= k, w # #O j , M = y(w # ,# # )and latest(y, w # ,M j ) # latest(y, w, M k )hold u (b) c) wu I= w O= u I= u O= w M 1 M 2 [4,6] 3,6] 2,7] w I= w O= M 1 [1,10] w I= O= w M 2 [1,20] u I= u O= M 1 [2,7] u I= O= u M 2 [4,5] (a) Figure 4: Examples of mod,A sets. Intuitively a timing failure occurs when a mod6q expects an input but it will not be given in time. Here there are several interpretations on in time . In type 1 timing failures it is the exact time (#) when the input is expected That is for each time ....

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T. Rokickiand C. Myers, Automatic verification of timed circuits,ComputerAidp Verification,LNCS 818 pp.468--480,1994.

....or delay padding one can restore the correct ordering of transitions and ensure the validity of almost any early enabling due to separation assumptions between outputs. The third requirement is, unfortunately, still far from realizable. Although good progress in this direction has been made [3, 12, 20, 1], we are still far from having an automated tool that can handle realistic circuits in a reasonable time in the presence of input non determinism. Hence for now this step is left to the designer s intuition and ability. For this paper, we have assumed that 1. All inputs to the circuit are slower ....

T. G. Rokicki and C. J. Myers. Automatic verification of timed circuits. In Proc. International Workshop on Computer Aided Verification, pages 468--480. Springer-Verlag, 1994.

.... work on efficient verification algorithms for real time systems includes the minimization algorithms of Alur et al. 1] and Yannakakis and Lee [25] Kang and Lee s reachability graphs [16] symbolic model checking [15, 19] and the partial order methods of Yoneda et al. 26] Rokicki and Myers [21], and McMillan and Ho [17] Safety verification problem We model a process as a transition system hS; S0 ; Ni where S is the underlying state space, S0 S is a set of initial states, and N S Theta S is a next state relation. A transition system describes a directed graph in the usual way. We ....

T.G. Rokicki and C.J. Myers. Automatic verification of timed circuits. In Proc. of 6th CAV, LNCS 818, Springer-Verlag, 1994.

....based system for the synthesis of timed asynchronous circuits. This work only treats the problem of transforming the initial specification to satisfy the timing constraints in a restrictive way. It does not add delay lines and does not change the edges on which signals are triggered. Rokicki [8] has proposed a timed Petri net model with relational semantics for general Petri nets. This work concentrates on an efficient method to find the states that are unreachable due to timing constraints and a way to check whether the Petri net is time consistent. It does not treat the problem of ....

....is proposed. The user should give an estimate of the delay of the logic, and the compiler uses this estimate during the synthesis of the STG. All the transformations on the STG are performed based on this estimate. Once the logic is technology mapped to a certain library a timing analysis tool [8] checks whether the assumptions made by the user are correct. If not, the user is forced to adapt the assumption made for the output delay relations or he may even be forced to change the original specification. So there is a loop over the synthesis process. This is schematically presented in ....

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T. Rokicki and C. Myers. Automatic verification of timed circuits. In CAV, 1994.

....of DBMs among the different discrete states, and finally, each discrete state is represented explicitly, thus these approaches are limited by the number of reachable states of the system. Several researchers have attempted to remedy these shortcomings, for example by using partial order methods [6,24,26] or by using approximate methods [3,5,27] Although these approaches do address the first problem, they are still susceptible to the last two problems since each state is represented explicitly. Using DDDs it is possible to combat all three problems since first, unlike DBMs, DDDs are not limited ....

T. G. Rokicki and C. J. Myers. Automatic verification of timed circuits. In D. L. Dill, editor, Computer Aided Verification (CAV), LNCS 818, pages 468--480, 1994.

....reuse of DBMs among the different discrete states, and (3) each discrete state is represented explicitly, thus these approaches are limited by the number of reachable states of the system. Several researchers have attempted to remedy these shortcomings, for example by using partial order methods [5, 18, 20] or by using approximate methods [3, 4, 21] Although these approaches do address problem (1) they are still susceptible to problems (2) and (3) since each state is represented explicitly. Using DDDs it is possible to combat all three problems since: 1) unlike DBMs, DDDs are not limited to ....

T. G. Rokicki and C. J. Myers. Automatic verification of timed circuits. In D. L. Dill, editor, Computer Aided Verification (CAV), number 818 in LNCS, pages 468--480, 1994.

.... states; and third, each discrete state is represented explicitly, thus these approaches are limited by the number of reachable states of the system (the well known state explosion problem) Several attempts have been made to remedy these shortcomings, for example by using partial order methods [6,22,23] or by using approximate methods [4,5,24] Although these approaches do address the first problem, they are still susceptible to the last two problems since each state is represented explicitly. Henzinger et al. 16] addresses the third problem by suggesting a symbolic approach to model checking ....

T. G. Rokicki and C. J. Myers. Automatic verification of timed circuits. In D. L. Dill, editor, Computer Aided Verification (CAV), number 818 in LNCS, pages 468--480, 1994.

....more difficult, motivating the need for formal verification. While numerous tools and techniques have been developed for verifying speed independent circuits [3, 4, 5, 6, 7, 8] verifying asynchronous circuits with timing assumptions has been rather limited. Burch [9, 10, 11] and Rokicki et al. [12] have verified gatelevel timed circuits and Yoneda et al. 13] have verified time Petri nets, but all their approaches have been limited to small examples due to the state explosion problem associated with their underlying explicit state techniques. To handle larger gate level circuits, Hamaguchi ....

....logic, dual rail logic, domino logic, or a mixture of these styles. Traditional synchronous latches, registers, and routing components are often used with only slight modifications. Timed controllers are made up of specialized memory elements, such as generalized C elements or static gates [12]. Typically, the representation of the implementation of a timed component is more complex than the representation of its specification. As an example of a timed system, consider the pausible clocking interface (PCI) illustrated in Fig. 1, which allows two different asynchronous domains to ....

[Article contains additional citation context not shown here]

T. G. Rokicki and C. J. Myers, "Automatic Verification of Timed Circuits," in Proc. of the Intl. Conf. on Computer Aided Verification, pp. 468-480, SpringerVerlag, 1994.

....the timed reachability graph, i.e. the states reachable given the timing information. It should be noted that Orbits is capable of analyzing a larger class of Petri net specifications than the one described here. Partial order techniques are also used in Orbits to reduce the state space explosion [20]. However, the time to construct the timed reachability graph for the eager stack increases exponentially with the size n. For n = 6 the time is 234 CPU seconds on a Decstation 5000 with 256 MB, i.e. two orders of magnitude slower than the CTSE algorithm. For n = 7, Orbits ran out of memory. 7 ....

T. G. Rokicki and C. J. Myers. Automatic verification of timed circuits. In D. L. Dill, editor, Computer Aided Verification (CAV), number 818 in Lecture Notes in Computer Science, pages 468--480, 1994.

....100 1000 10000 Petri net size, jF j Delta 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Delta 2 Fig. 5. Double logarithmic plot of CPU time for the two separation analyses as a function of the Petri net size, jF j. are also used in Orbits to reduce the state space explosion [17]. However, the time to construct the timed reachability graph for the eager stack increases exponentially with the stack size n. For n = 6 the time is 234 CPU seconds on a Decstation 5000 with 256 MB, i.e. two orders of magnitude slower than the CTSE algorithm. For n = 7, Orbits ran out of ....

T. G. Rokicki and C. J. Myers. Automatic verification of timed circuits. In D. L. Dill, editor, Computer-Aided Verification '94, pages 468--480.

....makes ensuring correctness via simulation more difficult, motivating the need for formal verification. While numerous tools and techniques have been developed for verifying speed independent circuits [3, 5, 8, 2, 12] verifying asynchronous circuits with timing assumptions has been rather limited. [4, 10, 13] have addressed verifying gate level timed circuits, but their techniques have been limited to small circuits due to the state explosion problem associated with their underlying explicit state techniques. The authors in [6] have addressed using implicit state techniques for gate level timed ....

T. G. Rokicki and C. J. Myers, "Automatic Verification of Timed Circuits, " in Proc. of the Intl. Conf. on Computer Aided Verification, pp. 468-480. Springer-Verlag, 1994.

....verification difficult. Furthermore, to our knowledge, partial order reduction has not yet been applied to it in the timed domain. As the third direction, we have proposed a framework of timed trace theoretic verification based on time Petri nets [10, 11, 12] The works most related to ours are [13, 14] and [15] However, in the former work, the models are restricted such that a single transition has only one behavioral place, and in the latter work, the notion of mirrors is not discussed. In [12, 16] safety failures and timing failures are defined, and the notion of pseudo failures is ....

T. Rokicki and C. Myers. Automatic verification of timed circuits. LNCS 818 Computer Aided Verification, pages 468--480, 1994.

....Program award INT 0087281, and SRC grant 99 TJ 694. partial order reduction has not yet been applied to it in the timed domain. As the third direction, we have proposed a framework of timed trace theoretic verification based on time Petri nets [10, 11, 12] The works most related to ours are [13, 14] and [15] However, in the former work, the models are restricted such that a single transition has only one behavioral place, and in the latter work, the notion of mirrors is not discussed. In [12, 16] safety failures and timing failures are defined, and the notion of pseudo failures is ....

T. Rokicki and C. Myers. Automatic verification of timed circuits. LNCS 818 Computer Aided Verification, pages 468--480, 1994.

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T.G. Rokicki and C.J. Myers, Automatic Verification of Timed Circuits, Proc. CAV'94, June, 1994.

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