Myers, C. J., Rokicki, T. G., Meng, T. H.-Y.: Automatic synthesis of gate-level timed circuits with choice, Advanced Research in VLSI, IEEE Computer Society Press, 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....asynchronous circuits. This paper focuses on techniques for the synthesis of control circuits. Currently, there are several academic tools that work at the logic level and attempt to optimize the resulting circuit by using variations of the state of the art Boolean minimization techniques [13, 6, 23]. Given that asynchronous circuits are typically modeled as concurrent systems, the existing synthesis approaches often suffer from the state explosion problem derived from concurrency. A crucial problem of most asynchronous logic synthesis tools is that they are not always capable of deriving an ....

Myers, C. J., Rokicki, T. G., Meng, T. H.-Y.: Automatic synthesis of gate-level timed circuits with choice, Advanced Research in VLSI, IEEE Computer Society Press, 1995.

....critical issues in modern VLSI circuits. This draws more interest in asynchronous designs as they compare favourably to synchronous circuits with respect to the above criteria. Two main approaches exist in asynchronous circuit design: direct syntax mapping [7, 11, 2, 14, 25] and logic synthesis [18, 5, 9]. In this paper, we focus on the direct mapping of concurrent speci cations, de ned as Petri nets (PN) into control circuits built of standard logic cells. The direct mapping approach has a long history originating from Hu man s work [12] where a method of the one relay per row realisation of ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In Advanced Research in VLSI, pages 4258. IEEE Computer Society Press, 1995.

....example, if a speci cation contains a counter and the counter is not represented as an explicit interface to a known counter implementation, then the direct mapping approach would generate a memory cell for every state of such a counter, which is not economical. Logic synthesis methods, such as [15, 7, 9], are better suited for such speci cations as they produce a near logarithmic state encoding and use signi cantly less memory elements (internal signals) This quality is often achieved at the expense of the lower speed, as at every stage of operation the circuit has to decode the state by ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In Advanced Research in VLSI, pages 4258. IEEE Computer Society Press, 1995.

....of timing assumptions to guarantee conformance of an implementation to its speci cation. 1 Introduction To increase performance, circuit designers are beginning to experiment with timed circuits. Timed circuits are a class of circuits that rely on timing information for correct functionality [1, 2, 3, 4]. This is evidenced by experimental designs such as the Intel RAPPID instruction length decoder in [5] and the IBM guTS microprocessor in [6] Although RAPPID is asynchronous and guTS is synchronous, both designs use formal timing assumptions to achieve better performance. Because these circuits ....

....in the TEL structure. Formally, an allowed trace of a TEL is a failure if any of the following conditions hold [49] 1. A constraint rule on an event is not satis ed when the event res; a ba b [0,0] c] 0,0] c] c] 0,0] c] 0,0] 7,9] 7,9] 7,9] 7,9] c [1,5] c [2,4] [ a b] a b c]d [2,4] a b] b) a) Figure 1: A TEL structure speci cation for a C element (a) and its environment (b) 4 2. A constraint rule on an event expires before the event res; 3. A disabling rule on an enabled place becomes false; 4. There are no enabled transitions (i.e. ....

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C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In Advanced Research in VLSI, pages 42-58. IEEE Computer Society Press, 1995.

.... the fast heuristics developed by [10] 11] and [12] and optimality (as in the case of the more powerful and expensive techniques developed by [13] and [14] Even though the underlying assumption may seem at the same time pessimistic (about gates) and optimistic (about wires) recent results [15] suggest that delayaware postoptimizations may further improve the quality of the synthesized results. Moreover, delay tuning [16] and low skew routing [17] may help satisfy the hypothesis about the low wire skew. The main problem of logic synthesis for speedindependent circuits is that they ....

C. Myers, T. Rokicki, and T. H.-Y. Meng, "Automatic synthesis of gate-level timed circuits with choice," in Adv. Res. VLSI, pp. 42--58, Mar. 1995.

....rates. However, since these techniques do not find the entire state space, they cannot be applied to synthesis. Logic synthesis algorithms for timed asynchronous circuits require that all of the boolean states allowed by the state space are found in order to create a correct logic implementation [52]. If the synthesis algorithm is given an incomplete state space, it cannot be guaranteed to generate logic that correctly responds to all inputs to the circuit. Orbits, presented by Myers and Rokicki in [58, 59, 53] takes a somewhat different approach. It reduces the number of regions per ....

Myers, C. J., Rokicki, T. G., and Meng, T. H.-Y. Automatic synthesis of gate-level timed circuits with choice. In 16th Conference on Advanced Research in VLSI (1995), IEEE Computer Society Press, pp. 42--58.

....that we generate must be synthesized in such a way to guarantee that it operates correctly given that the delay for this event always falls in these bounds. The timing analysis algorithms and synthesis algorithms necessary to generate such timed circuits have been the subject of numerous papers [19, 20, 18, 3]. Finding these timing constraints, or the delay bounds to associate with the transitions on these signals is not a trivial task. The timing constraints for input signal transitions can usually be determined from interface specifications or datapath delay estimates. The timing constraints for ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng, Automatic synthesis of gatelevel timed circuits with choice, in 16th Conference on Advanced Research in VLSI, IEEE Computer Society Press, 1995, pp. 42--58.

....but it does not address the state explosion problem inherent in discrete time. The geometric region method, where timing information is stored as a constraint matrix representing relationships between signal transition times, has been shown to be an efficient way to represent a timed state space [4, 30, 35, 36]. However, even with a region based representation, the memory required to store such a state space explicitly can be prohibitive for large designs. In many domains, implicit methods have been shown to significantly reduce memory usage [9] Since state space exploration is such a memory intensive ....

....enabled in the same direction or stable at the final value may be included. In a SC circuit, some of those states may need to be excluded to guarantee hazard freedom. The correctness constraints discussed here were developed in [3] for speed independent circuits and extended to timed circuits in [30]. 3.3.1 gC cover violations In a gC implementation, the allowed growth regions include the remainder of the excitation space and the entire quiescent space for the corresponding signal transition. In other words, correct covers must satisfy the following covering constraint: ER C Phi ES [ ....

Myers, C. J., Rokicki, T. G., and Meng, T. H.-Y. Automatic synthesis of gate-level timed circuits with choice. In Proc. 16th Conf. on Advanced Research in VLSI (1995), IEEE Computer Society Press, pp. 42--58.

....solution to synchronous design challenges. Many techniques exist for designing asynchronous circuits and each has its own merits [7] However, the work presented in this thesis relies upon, and is an extension to, a specific class of asynchronous circuits called timed asynchronous circuits [13, 14, 15]. Important to this research is a general notion of a timed circuit and its position relative to other asynchronous methodologies. Timed circuits uphold a more realistic model of circuit behavior. Rather than restricting inputs and outputs to occur in tightly ordered bursts or to assume a possibly ....

Myers, C. J., Rokicki, T. G., and Meng, T. H.-Y. Automatic synthesis of gate-level timed circuits with choice. In Advanced Research in VLSI (1995), IEEE Computer Society Press, pp. 42--58.

....makes ensuring correctness via simulation more difficult, motivating the need for formal verification. While numerous tools and techniques have been developed for verifying speed independent circuits [3, 5, 8, 2, 12] verifying asynchronous circuits with timing assumptions has been rather limited. [4, 10, 13] have addressed verifying gate level timed circuits, but their techniques have been limited to small circuits due to the state explosion problem associated with their underlying explicit state techniques. The authors in [6] have addressed using implicit state techniques for gate level timed ....

....logic, dual rail logic, domino logic, or a mixture of these styles. Traditional synchronous latches, registers, and routing components are often used with only slight modifications. Timed controllers are made up of specialized memory elements, such as generalized C elements or static gates [10, 17]. Typically, the representation of the implementation of a timed component is more complex than the representation of its specification. As an example of a timed system, consider the pausibleclocking interface (PCI) illustrated in Fig. 1, which allows two different asynchronous domains to ....

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C. J. Myers, T. G. Rokicki, T. H.-Y. Meng, "Automatic Synthesis of GateLevel Timed Circuits with Choice," in Chappel Hill Conf. on Advanced Research in VLSI, ARVLSI `95, March 1995.

....its import in the design process. 1 Introduction Many techniques exist for designing asynchronous circuits and each has its own merits [1] However, the work presented in this paper relies upon, and is an extension to, a specific class of asynchronous circuits called timed asynchronous circuits [2, 3, 4]. Important to this research is a general notion of a timed circuit and its position relative to other asynchronous methodologies. Timed circuits uphold a more realistic model of circuit behavior. Rather than restricting inputs and outputs to occur in tightly ordered bursts or to assume a possibly ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In Advanced Research in VLSI, pages 42--58. IEEE Computer Society Press, 1995.

....solution to synchronous design challenges. Many techniques exist for designing asynchronous circuits and each has its own merits [7] However, the work presented in this thesis relies upon, and is an extension to, a speci c class of asynchronous circuits called timed asynchronous circuits [13, 14, 15]. Important to this research is a general notion of a timed circuit and its position relative to other asynchronous methodologies. Timed circuits uphold a more realistic model of circuit behavior. Rather than restricting inputs and outputs to occur in tightly ordered bursts or to assume a possibly ....

Myers, C. J., Rokicki, T. G., and Meng, T. H.-Y. Automatic synthesis of gate-level timed circuits with choice. In Advanced Research in VLSI (1995), IEEE Computer Society Press, pp. 42-58.

....both a set of red rules, R f , and information about the time relationships between the rules currently in Rm . These time relationships are represented with geometric regions, which were rst introduced in [9, 10, 11] This approach has been shown to be ecient for timed state space exploration [12, 8, 13]. When the geometric region approach is used for timing analysis, a constraint matrix M speci es the maximum di erence in time between the enabling times of all the currently enabled rules. The 0th row and column of the matrix contain the separations between the enabling times of each enabled rule ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In Advanced Research in VLSI, pages 42-58. IEEE Computer Society Press, 1995.

....region for any set of firing sequences that differ only in the firing order of concurrent events. This algorithm is shown in [15] to result in very few geometric regions per untimed state. The entire timed state space is explored, so it can be used for both verification [15] 16] and synthesis [17]. However, it is limited to specifications where the firing time of an event can only be controlled by a single predecessor event. This is known as the single behavioral place restriction. In [18] we presented an approximate algorithm for exploring the entire state space with POSETs on a general ....

....presets and either transition can fire. Once a choice is made, the other transition loses its chance to fire. It is necessary to note at this point the key difference between the standard timed Petri net semantics used in this paper and the orbital net specification method used in [15] 16] [17]. Although orbital nets are similar to timed Petri nets, they have some important differences. The difference that is relevant to timing analysis is that the places of an orbital net are labeled as either behavioral or constraint and only a single behavioral place can be in the preset of any ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In Advanced Research in VLSI, pages 42--58. IEEE Computer Society Press, 1995.

....solution to synchronous design challenges. Many techniques exist for designing asynchronous circuits and each has its own merits [8] However, the work presented in this thesis relies upon, and is an extension to, a specific class of asynchronous circuits called timed asynchronous circuits [12, 14, 16]. Important to this research is a general notion of a timed circuit and its position relative 2 to other asynchronous methodologies. Timed circuits uphold a more realistic model of circuit behavior. Rather than restricting inputs and outputs to occur in tightly ordered bursts or to assume a ....

Myers, C. J., Rokicki, T. G., and Meng, T. H.-Y. Automatic synthesis of gate-level timed circuits with choice. In Advanced Research in VLSI (1995), IEEE Computer Society Press, pp. 42--58.

No context found.

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng, "Automatic synthesis of gate-level timed circuits with choice," in 16th Conference on Advanced Research in VLSI. 1995, pp. 42--58, IEEE Computer Society Press.

....needs to be computed, it is not appropriate for timed state space exploration. Also, while CTSE does handle choice, it is limited to unique, free and extended free choice [7] Orbits [14] is specifically designed to do timed state space exploration and has been applied to timed circuit synthesis [13]. It uses geometric regions to keep track of the timing information relevant to the current marking of the graph and uses these regions to determine which events are timed enabled. Only local information about timing relationships is necessary to find the next set of timed states. This allows ....

.... be condensed into a single contiguous geometric region that contains all of them, producing a large reduction in the number of timed states generated [14] While worst case behavior of geometric timing is actually worse than the discrete method it has been shown that it can work well in practice [15, 13]. When using geometric regions for timing analysis in the generic algorithm, we define TI to be a constraint matrix M that specifies the maximum differences in time between the firings of the enabling events of all the rules in R en . The 0th row and column of the matrix contain the separations ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In Proc. 16th Conf. on Advanced Research in VLSI, pages 42-- 58. IEEE Computer Society Press, 1995.

....to compute the set of satisfied rules, R s . Only rules in R s are allowed to fire and cause a transition to another state. Our timing information is represented with geometric regions, first introduced in [22, 23, 24] This approach has been shown to be efficient for timed state space exploration [25, 26, 18] and can be easily modified to analyze TEL structures without any substantial increase in synthesis time. The geometric region based timing analysis method for timed ER structures is based on keeping track of the relationships between the enabling times of a set of rules. The only change that ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In Proc. 16th Conf. on Advanced Research in VLSI, pages 42--58. IEEE Computer Society Press, 1995.

....but it does not address the state explosion problem inherent in discrete time. The geometric region method, where timing information is stored as a constraint matrix representing relationships between signal transition times, has been shown to be an efficient way to represent a timed state space [3, 14, 16, 17]. However, even with a region based representation, the memory required to store such a state space explicitly can be prohibitive for large designs. In many domains, implicit methods have been shown to significantly reduce memory usage [7] Since timed state space exploration is such a memory ....

....enabled in the same direction or stable at the final value may be included. In a SC circuit, some of those states may need to be excluded to guarantee hazard freedom. The correctness constraints discussed here were developed in [1] for speed independent circuits and extended to timed circuits in [14]. In a gC implementation, the allowed growth regions include the remainder of the excitation space and the entire quiescent space for the corresponding signal transition. In other words, correct covers must satisfy the following covering constraint: ER C Phi ES [ QS. The boolean equation ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In Proc. 16th Conf. on Advanced Research in VLSI, pages 42--58. IEEE Computer Society Press, 1995.

....0 C 1 : Cm ) In order to create a valid timed circuit implementation, it is necessary to define the states a cover must include, may include, and may not include. The correctness constraints discussed here were developed in [1] for speed independent circuits and extended to timed circuits in [12]. In a gC implementation, the allowed growth regions include all states in ES and QS for the corresponding signal transition. This covering constraint prevents the gate from being pulled up and down simultaneously or changing values at the wrong time. In a SC implementation, additional internal ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In 16th Conference on Advanced Research in VLSI, pages 42-- 58. IEEE Computer Society Press, 1995.

.... the firing time of an event can only be controlled by a single predecessor event (known as the single behavioral place (or rule) restriction) This restriction can be worked around with graph transformations, but the graph transformations add n new rules for each event with n behavioral rules[15, 16]. In [17] we presented an approximate algorithm for exploring the entire state space with POSETs on a general class of specifications, lifting the single behavioral rule restriction. However, it may generate regions that are larger than necessary. This paper presents a new algorithm for timed ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In 16th Conference on Advanced Research in VLSI, pages 42--58. IEEE Computer Society Press, 1995.

....of the excitation region. The cover of a set region C(u ; k) or a reset region C(u #; k) is a set of states for which the corresponding cube in the implementation evaluates to one. In order for a cover to lead to a hazard free implementation, it must satisfy certain correctness constraints [7, 54]. These constraints guarantee that any gate in the implementation only changes when it is actively driving the output signal to change. This ensures that the transition of the gate is acknowledged. First, a correct cover needs to satisfy a covering constraint which says that the reachable states ....

....procedure just described. Otherwise, the falling transition of the new signal is placed between all the trigger signals for the original falling (rising) transition and the original falling (rising) transition itself. This new specification is then resynthesized using the automatic procedure from [54] to produce a new hazard free timed circuit implementation. If the new implementation does not have any high fanin gates, the decomposition is successful. Otherwise, the procedure must repeat using a different decomposition for each remaining high fanin gate. Returning to the tsbm, we apply our ....

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C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In 16th Conference on Advanced Research in VLSI, pages 42--58. IEEE Computer Society Press, 1995.

....timing information into the specification and utilizing it throughout the design procedure to optimize the implementation. Timed circuits can be significantly smaller and faster than those produced using traditional methods, and they are more reliable than those produced using ad hoc methods [1]. The specification of timing constraints also facilitates a natural interaction between synchronous and asynchronous circuits. Our previous work introduced automatic procedures for the synthesis and verification of gate level timed circuits [2, 3, 1] and demonstrated that timed designs can be ....

....reliable than those produced using ad hoc methods [1] The specification of timing constraints also facilitates a natural interaction between synchronous and asynchronous circuits. Our previous work introduced automatic procedures for the synthesis and verification of gate level timed circuits [2, 3, 1] and demonstrated that timed designs can be significantly smaller and faster than designs generated using other asynchronous design methodologies. The timed designs, however, are synthesized without considering explicitly the available gate library. In particular, these designs may require gates ....

[Article contains additional citation context not shown here]

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In 16th Conference on Advanced Research in VLSI, pages 42--58. IEEE Computer Society Press, 1995.

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