B. Juurlink, D. Tcheressiz, S. Vassiliadis, and H. Wijshoff, "Implementation and evaluation of the complex streamed instruction set," Proc. Int. Conf. on Parallel Architectures and Compilation Techniques, Sep. 2001. Home/Search Document Details and Download
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Current Research Efforts in Media ISA Development - Lappalainen, Liuha, Hämäläinen (Correct)
....memory architecture. The decision to not use any registers for stream data was motivated by the intention not to have an architectural constraint on the sub word size, and by the observation that vector registers are not always able to exploit data reuse in multimedia applications while caches are [11]. 4. OPTIMIZATION OF SUBWORD SIZES Brooks and Martonosi propose hardware mechanisms that dynamically recognize and capitalize on narrow bit width (16 bits or less) instances in programs without any programmer intervention or compiler support [1] Scott and Davidson extend the work of Brooks and ....
....0.9 2.5 1.5 2.2 MOM and reduction operations [6] Corbal et al. MIPS R10000 MMX MDMX Jinks simulator IDCT, RGB2YCC, SAD,etc. 1.5 n a 2 SMT MMX like ISA extensions [18] Oehring et al. PowerPC 604 MMX execution based simulator hand coded MPEG 2 decoder n a 1.7 2. 5 2,3,4 CSI [11] Juurlink et al. Portable ISA VIS SimpleScalar [2] JPEG MPEG 2 codecs 4.0 1.1 1.4 Conditional streams [12] Kapasi et al. Imagine [13] simulator polygon rendering see [12] 1.8 3 Density time conditional processing [26] Smith et al. VL time implementation simulated vector machine loop ....
B. Juurlink et al., "Implementation and Evaluation of the Complex Streamed Instruction Set," Proc. Intl. Conf. on PACT, 2001.
Hardware Support to Reduce Overhead in Fine-Grain Media Codes - Talla, John, Burger (2001) (Correct)
....frequencies. Similarly, the address generation stage needs to be divided into three pipe stages to achieve frequencies greater than 1 GHz. 6 Related Work Corbal et al. 36] proposed to exploit DLP in two dimensions instead of one dimension as in current SIMD extensions. Vassiliadis et al. 37][38] have concurrently proposed the Complex Streamed Instruction set (CSI) that can exploit two levels of looping. Though they are able to eliminate some overhead because each of their complex instructions can eliminate two loops, our results show that more overhead can be eliminated with 5 loops. Lee ....
B. Juurlink, D. Tcheressiz, S. Vassiliadis, and H. Wijshoff, "Implementation and evaluation of the complex streamed instruction set," Proc. Int. Conf on Parallel Architectures and Compilation Techniques, Sep. 2001.
Architectural Techniques to Accelerate Multimedia Applications on.. - Talla (2001) (Correct)
....(conventional SIMD extensions) a simple in order long vector allows for potential saving in chip area and achieves better multimedia performance. However, it is important to have a general purpose processor to achieve sustained performance on different domains of workloads. Vassiliadis, et al. [50][106] have proposed the Complex Streamed Instruction Set (CSI) to enhance an existing out of order GPP. A stream computa 30 tion instruction can capture two levels of loop nesting. Vermuelen, et al. 107] describe how DCT, Reed Solomon code, and other similar media oriented operations can be ....
B. Juurlink, D. Tcheressiz, S. Vassiliadis, and H. Wijshoff, "Implementa- tion and evaluation of the complex streamed instruction set," Proc. Int. Conf. on Parallel Architectures and Compilation Techniques, Sep. 2001, to appear.
Architectural Support for 3D Graphics in the.. - Cheresiz.. Self-citation (Juurlink Vassiliadis Wijshoff) (Correct)
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B. Juurlink, D. Tcheressiz, S. Vassiliadis, and H. Wijshoff. Implementation and Evaluation of the Complex Streamed Instruction Set. In Proc. Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), 2001.
Architectural Support for 3D Graphics in the.. - Cheresiz.. Self-citation (Juurlink Vassiliadis Wijshoff) (Correct)
No context found.
B. Juurlink, D. Tcheressiz, S. Vassiliadis, and H. Wijshoff. Implementation and Evaluation of the Complex Streamed Instruction Set. In Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), 2001.
Implementation of a Streaming Execution Unit - Cheresiz, Juurlink.. (2002) Self-citation (Juurlink Vassiliadis Wijshoff) (Correct)
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B. Juurlink, D. Tcheressiz, S. Vassiliadis, and H. Wijshoff. Implementation and Evaluation of the Complex Streamed Instruction Set. In Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), 2001.
Performance Benefits of Special-Purpose Instructions.. - Cheresiz, Juurlink.. Self-citation (Juurlink Vassiliadis) (Correct)
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B. Juurlink, D. Tcheressiz, S. Vassiliadis, and H. Wijshoff. Implementation and Evaluation of the Complex Streamed Instruction Set. In Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), 2001.
Bottlenecks in Multimedia Processing with SIMD Style.. - Talla, John, Burger (2003) (Correct)
No context found.
B. Juurlink, D. Tcheressiz, S. Vassiliadis, and H. Wijshoff, "Implementation and evaluation of the complex streamed instruction set," Proc. Int. Conf. on Parallel Architectures and Compilation Techniques, Sep. 2001.
Unknown - (2001) (Correct)
No context found.
Ben Juurlink, Dmitri Tcheressiz, Stamatis Vassiliadis, and Harry Wijshoff. Implementation and evaluation of the complex streamed instruction set. To appear in PACT-01, Barcelona, September 2001.
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