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R.P. Koganti and G. Kedem, "WCDRAM: A Fully Associative Integrated Cached-DRAM with Wide Cache Lines," Proc. Fourth IEEE Workshop Architecture and Implementation of High Performance Comm. Systems, 1997.

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Design and Optimization of Large Size and - Low Overhead Off-Chip   (Correct)

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R.P. Koganti and G. Kedem, "WCDRAM: A Fully Associative Integrated Cached-DRAM with Wide Cache Lines," Proc. Fourth IEEE Workshop Architecture and Implementation of High Performance Comm. Systems, 1997.


Cached DRAM for ILP Processor Memory Access Latency Reduction - Zhang, Zhu, Zhang (2001)   (2 citations)  (Correct)

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R.P. Koganti, and G. Kedem, WCDRAM: A Fully Associative Integrated Cached-DRAM with Wide Cache Lines, tech. report CS1997

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