V. Dai and A. Zakhor, "Lossless Layout Compression for Maskless Lithography Systems", Proc. Emerging Lithographic Technologies IV, Santa Clara, February 2000, SPIE Volume 3997, pp. 467-477. Home/Search Document Details and Download
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Data Handling Issues in Maskless Lithography - Wild, Wongkomet (Correct)
....is to optimize the circuitry to minimize the area, power consumption and maximize the speed in the order of importance. The design did not take into account how to transfer 5 bit grayscale data to the mirrors, which as will be shown can be a major contributor to the area and power figures. In [2], non systolic architecture was proposed. 128 history buffers were implemented to improve the compression ratio. This chip was fabricated using CMOS 2 micron technology. However, the throughput is only 20Mcharacter s, which is much slower than what is needed in the maskless lithography ....
V. Dai, A. Zakhor. "Lossless Layout Compression for Maskless Lithography Systems", Proceedings of the SPIE Emerging Lithographic Technologies IV, vol. 3997, March 2000.
Lossless Compression Techniques for Maskless Lithography Data - Dai, Zakhor Self-citation (Dai Zakhor) (Correct)
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V. Dai and A. Zakhor, "Lossless Layout Compression for Maskless Lithography Systems", Emerging Lithographic Technologies IV, Elizabeth A. Dobisz, Editor, 3997, pp. 467-477, SPIE, 2000.
Evaluation of the New OASIS Format for Layout Fill.. - Chen, Kahng, Robins.. (2004) (Correct)
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V. Dai and A. Zakhor, "Lossless Layout Compression for Maskless Lithography Systems", Proc. Emerging Lithographic Technologies IV, Santa Clara, February 2000, SPIE Volume 3997, pp. 467-477.
Area Fill Generation With Inherent Data Volume Reduction - Yu Chen Andrew (2003) (Correct)
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V. Dai and A. Zakhor, "Lossless Layout Compression for Maskless Lithography Systems", Proc. Emerging Lithographic Technologies IV, Santa Clara, February 2000, SPIE Volume 3997, pp. 467-477.
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