R. P. S. Sidhu, A. Mei, S. Wadhwa, and V. K. Prasanna. A self-recongurable gate array architecture. In FPGA '99. Proceedings of the  Home/Search   Document Not in Database   Summary   Related Articles

....the logic cell bits written into these locations control the functionality of the logic cell. The con gured logic writes bits that con gure the logic cell as an AND gate into the above con guration memory locations. Finally, it switches to the context on which the gate was con gured. Please see [6] for a detailed description of the SRGA device and its capabilities, including row and column routing using self recon guration. 4.2 NFA Construction using SelfRecon guration Figure 10 shows the algorithm that reads a regular expression and constructs the corresponding NFA using selfrecon ....

....placing the logic structure for in the same column. The numbers at the end of each line in Figure 10 indicate the number of clock cycles required to complete the operation on that line. Counter increments occur in parallel with other operations and so take zero clock cycles. As described in [6], any row or column routing operation on the SRGA takes 4 clock cycles.The row route and col route operations create bidirectional connections. Also, it takes 2 clock cycles to switch to the context with the routing logic and back to the current context. Thus each routing operation takes 10 clock ....

R. P. S. Sidhu, A. Mei, S. Wadhwa, and V. K. Prasanna. A self-recongurable gate array architecture. In FPGA '99. Proceedings of the

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