S.R. Nassif and J.N. Kozhaya, "Fast power grid simulation," Proc. of Design Automation Conference, 2000, pp. 156-161.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....and complexity grow with UDSM integration. Without the purpose of giving an exhaustive exploration of noise in deep submicron circuits (for which see also [7, 9, 32, 37] in the following we will consider the relationship among high performance issues and noise e#ects due to power supply lines [19, 20, 29, 31, 28]. Transistor sizes scaling down implies overall an increased number of gates without total chip area changes. Considering a standard cell layout style, this means a greater number of gates on a row; this fact is a#ected also by the number of circuit blocks used if a system on a chip is ....

....the only issue, but the waveform is needed for actual activity computation and for derivative evaluation in the switching noise (LdI dt) term. Di#erent works have addressed this point, first for power estimation evaluation, and, recently, for IR drop analysis and for power supply lines design [28, 31, 12]. Considering an exhaustive simulation extremely expensive to be inserted in a cad design algorithm, more approximated di#erent evaluation techniques have been developed. One is the generation of test vectors able to find a small input set producing a worst switching activity in the circuit, but ....

S. Nassif and J. Kozhaya. Fast power grid simulation. In Proc. of DAC00, Design Automation Conference, Loas Angeles, CA, USA, 2000. 38

....sources modeling the switching activity of circuit blocks, and capacitors that model decoupling and intrinsic capacitance to simulate the dynamic behaviors. To accommodate the millions of resistors in such power ground network models, hierarchical approaches [5] and multigrid like techniques [6] have been developed. An obvious solution to the IR drop problem is to size up the wires in a power ground distribution network. However, as the width and thickness of the wires increase, the inductance effect becomes evident for the on chip metal layers. Furthermore, for high performance systems ....

....mutual susceptance, can be transformed into a combined companion model through a Norton to Thevinin equivalent circuit transformation. This enables elimination of one node for each segment. Also, it opens the door for further speedup through either a hierarchical [5] or a multigrid like approach [6], since the symmetrical positive definiteness of the simulation formulation which previously existed only for RC circuits, is preserved for RCS circuits here [12] 4 EXPERIMENTAL RESULTS AND DISCUSSIONS In order to test the methodology presented in Section 2 and 3, we created power grids ....

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S. R. Nassif and J. N. Kozhaya, "Fast Power Grid Simulation," in Proc. 37-th DAC, pp. 156-161, June 2000.

....models for the network. A 3 stage IR drop analysis methodology during the whole design process is presented in [DPB 98] ZPS 00] propose a hierarchical analysis technique and a novel sparsification method based on 0 1 integer linear programming. A PDE like multigrid method is proposed in [NK00] to perform both DC and transient simulation of power grids efficiently. Each of the above methodologies aims at speeding up the analysis and predicting the power grid performance properly. Other related work on optimizing P G networks includes [SVR 94, SRC95, TSL 99] which use techniques ranging ....

S. R. Nassif, J. N. Kozhaya, "Fast power grid simulation," In Proceedings of the ACM/IEEE Design Automation Conference, pp. 156-161, 2000.

....noise, estimation of the switching noise in a P G network is necessary at an early phase of the design process so that different design schemes can be explored to relieve the noise issue. Recently, several approaches have been proposed to estimate the power supply noise [6] 7] 8] 14] 12] [13]. Chen and Ling [6] proposed an approach to estimate the power supply noise based on an integrated package level and chip level power bus model. Chang, Gupta, and Breuer [7] proposed an analytical model to estimate the # This research is supported in part by SRC (99 TJ 689) NSF (CAREER Award ....

....computation cost is O#n 3 #, which is formidable for large P G networks. To reduce the computation complexity, 12] proposed a divide and conquer approach to solve the system in a hierarchical way by partitioning the system into small subsystems and modeling the sub networks with macromodels. [13] proposed an (partial differential equation) PDE like multigrid method to solve the problem on a coarse grid and then map the solution back to the fine grid using linear interpolation. In this paper, we propose an approach for the analysis of power supply noise in the frequency domain for a P G ....

S. Nassif, J. Kozhaya, "Fast Power Grid Simulation," Proc. Design Automation Conference, pp. 156-161, 2000.

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S. R. Nassif and J. N. Kozhaya. Fast Power Grid Simulation. In Proc. Design Automation Conference, pages 156--161, Los Angeles, CA, June 2000.

....voltage sources. By applying the Backward Euler integration formula [16] to Eq. 5) we have: G C h)x(t h) u(t h) x(t)C h (6) Where h is the time step for the transient analysis. If h is kept constant, only a single initial factorization of the matrix G C h is required (as is done in [15], 19] leading to an e#cient algorithm for transient analysis where each time step requires only a forward backward solution step. After the transient analysis of the circuit, the voltage waveform at every node is known. Given that the treatment for nodes on the ground grid is completely ....

S. R. Nassif and J. N. Kozhaya. Fast Power Grid Simulation. In Proc. Design Automation Conference, pages 156--161, Los Angeles, CA, June 2000.

....once voltage drops exceed certain designer specified thresholds, there is no guarantee that the circuit will operate properly [1] 2] 3] Thus, it is clear that in modern VLSI circuits, power grids are becoming performance limiting factors. Consequently, e#cient analysis of power grids [4], 5] is necessary for both (1) predicting the performance and (2) improving the performance if necessary. Because of the large dimensions of power grids in modern VLSI circuits, existing anal J. N. Kozhaya is with IBM Corp. 1000 River St. Essex Junction, VT 05452. He was with the ECE ....

S. R. Nassif and J. N. Kozhaya. Fast power grid simulation. In Proceedings of DAC, 2000.

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S.R. Nassif and J.N. Kozhaya, "Fast power grid simulation," Proc. of Design Automation Conference, 2000, pp. 156-161.

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S. R. Nassif and J. N. Kozhaya, "Fast power grid simulation ", Proc of Design Automation Conf., pp.156161, 2000.

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S. R. Nassif and J. N. Kozhaya. Fast Power Grid Simulation. In Proc. Design Automation Conference, pages 156--161, Los Angeles, CA, June 2000.

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S. R. Nassif and J. N. Kozhaya, "Fast power grid simulation", in Proc. Design Automation Conference, June 2000, pp. 156--161.

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