MIRANDA,M.A.,CATTHOOR,F.V.M.,JANSSEN, M., AND DE MAN, H. J. 1998. High-level address optimization and synthesis techniques for data-transfer-intensive applications. IEEE Trans. Very Large Scale Integr. Syst. 6, 4, 677--686. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Performance-Area Trade-Off of Address Generators for.. - Hettiaratchi, Cheung, .. (2002) (Correct)
....cost. ZIPPO tool which is integrated with PHIDEO considers several address streams accessing different memory modules on chip, and synthesises an address generator that is area optimized by sharing hardware [5] The combined ADOPT methodology for address generator synthesis described in [8] is a general framework for optimizing address generators. ADOPT considers both counter based and arithmetic based address generator styles and also considers hardware sharing. Schmit and Thomas employ some interesting properties of the exclusive OR function to overcome the offset addition problem ....
M. Miranda, F. Catthoor, and M. J. H. D. Man. Highlevel address optimization and synthesis techniques for datatransfer -intensive applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(4):677 -- 686, Dec. 1998.
Synthesis of Pipelined Memory Access Controllers for Streamed.. - Park, Diniz (2001) (4 citations) (Correct)
....Panda et al. 8,9] refined this approach by defining a time constrained based specification of the a centralized scheduler for handling external memory operations. Catthoor, Balasa et al. developed and evaluated memory optimizations for embedded systems for a particular application set [1,2,6]. This research focuses on optimizations to minimize memory area and power consumption. Catthoor also proposed a data packing scheme to reduce memory bandwidth requirements for dynamic data structure. Wuytack et al. suggested minimizing memory bandwidth requirements [14] by mapping highly accessed ....
M. Miranda, F.Catthoor, M. Janssen and H. DeMan, "High-level address optimization and synthesis techniques for data-transferintensive applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(4), Dec. 1998, pp. 677 --686.
High-Level Synthesis of Control and Memory Intensive Applications - Ellervee (2000) (Correct)
....organization exploration environment Matisse is a design flow intended for system exploration and synthesis of embedded systems characterized by dynamic data storage and intensive data transfer. The four main steps of the Matisse design flow are as follows (see also Figure 4. 1) WCD96] MCJ96] MCJ98] SWC97] SYM98] During dynamic memory management refinement the actual structures of dynamic data types and virtual memories is decided. The goal of task concurrency management is to meet the overall real time requirements imposed to the application being designed. Physical memory ....
M. Miranda, F. Catthoor, M. Janssen, H. De Man, "High-Level Address Optimization and Synthesis Techniques for Data-Transfer-Intensive Applications", IEEE Trans. on VLSI Syst., Vol.6, No.4, Dec. 1998.
Data and Memory Optimization Techniques for Embedded.. - Panda, Catthoor, Dutt, .. (2001) (14 citations) Self-citation (Catthoor) (Correct)
No context found.
MIRANDA,M.A.,CATTHOOR,F.V.M.,JANSSEN, M., AND DE MAN, H. J. 1998. High-level address optimization and synthesis techniques for data-transfer-intensive applications. IEEE Trans. Very Large Scale Integr. Syst. 6, 4, 677--686.
A Systematic Approach to Reduce the System Bus.. - Danckaert.. Self-citation (Catthoor De man) (Correct)
No context found.
M.Miranda, F.Catthoor, M.Janssen, H.De Man, "High-level address optimization and synthesis techniques for data-transfer intensive applications", IEEE Trans. on VLSI Systems, Vol.6, No.4, pp.677-686, Dec. 1998.
Low-Power Implementation Of An Ofdm Based Channel.. - de Beeck, Ghez.. Self-citation (Miranda Catthoor) (Correct)
....can benefit from such a transformation, but the problem was especially noticeable in the aggressive case, simply because the cache pressure is higher there. 4.3. High level address and processor specific optimizations All code versions have been complemented with high level address optimizations[8, 9]. These are mainly devoted to further reduce execution time of cycles spend on address arithmetic computations. In addition some TriMedia specific foregroundmemory oriented transformations have been considered. More specifically inlining and loop unrolling to move small arrays in the critical ....
M.Miranda, F.Catthoor, M. Janssen, H.De Man, High-Level Address Optimization and Synthesis Techniques for Data-Transfer Intensive Applications, IEEE Trans. on VLSI Systems, no.4, vol.6, Dec. 1998.
Exploiting Data Transfer Locality in Memory Mapping - Ellervee, Miranda.. (1999) (2 citations) Self-citation (Miranda Catthoor) (Correct)
....group pre packing Matisse System Figure 1. Matisse design flow 3. Matisse environment Matisse is a design flow intended for system exploration and synthesis of embedded systems characterized by dynamic data storage and intensive data transfer. The four main steps of the Matisse design flow [13, 14, 19, 9] are as follows (see also Figure 1) # During dynamic memory management the actual structures of dynamic data types and virtual memories are decided. # The goal of task concurrency management is to meet the overall real time requirements imposed to the application being designed. # Physical ....
M. Miranda, F. Catthoor, M. Janssen, H. De Man, "HighLevel Address Optimization and Synthesis Techniques for Data-Transfer Intensive Applications", IEEE Trans. on VLSI Systems, no.4, vol.6, pp.677-686., Dec. 1998.
Mesh Partitioning Approach to Energy Efficient Data Layout - Sambuddhi Hettiaratchi Peter (2003) (Correct)
No context found.
M. Miranda, F. Catthoor, M. Janssen, and H. D. Man. Highlevel address optimization and synthesis techniques for datatransfer -intensive applications. IEEE Trans. on VLSI Systems, 6(4):677 -- 686, Dec. 1998.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC