G. Nicolescu, S. Yoo, and A. A. Jerraya, "Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design", to appear in Proc. Design Automation and Test in Europe, 2001.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....and conservation analysis. 1. Introduction Complex Systems on Chip (SoC) often include a number of pre designed hardware blocks. The performance of these systems depend significantly on the synchronization overhead caused by the SoC architecture, bus protocol and shared memory access [1] [5]. There is a huge design space related to the communication architecture. For example, the communication model could use message passing or shared memory; the single address space of the shared memory could have centralized or distributed physical memory; the bus might have different widths, ....

G. Nicolescu, S. Yoo and A.A. Jerraya, "Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design," In proc. of Design Automation and Test in Europe pp.754-759, 2001

....SoC DESIGN This section introduces a system design methodology aimed at solving all the limitations of current interface based design methods. This is a multiprocessor SoC design approach using a communication refinement methodology based on virtual components [12] 13] 14] 15] 16] [17] [18] 19] In this methodology, the system is described as a set of virtual components interconnected via channels. A virtual component consists of a wrapper and an internal component. The internal component corresponds to a heterogeneous component (e.g. a DSP or an IP) and the wrapper adapts ....

....the translation of the extended SystemC specification produces the first Colif model, which represents the virtual architecture, and is annotated with configuration parameters. In this design environment, there are three tools for automatic generation of wrappers: co simulation wrapper generator[ 17], hardware wrapper generator[ 19] and the software wrapper generator [ 16] Colif Fig. 7. Design environment for multiprocessor SoC I gene;n I Co simulation library Rlrchitecture pP2 I Comm. network I J Co sim. 1 generation OS librarv c. Processor I Application SwWrapper ....

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G. Nicolescu, S. Yoo, and A. A. Jerraya, Mixed-level Cosimulation for Fine Gradual Refinement of Communication in SoC Design, Proc. of Design Automation & Test in Europe (DATE), 2001.

....specified the control sub system in SystemC and the electro mechanical part in Matlab. For the behavior of optical devices (mirrors, lens, beam generators and detectors) we used C models from the libraries of Chatoyant [15] 3. Cosimulation environment The cosimulation environment [12] 13] [14] starts with a system model given as a netlist of heterogeneous components and enables automatic generation of simulation models for heterogeneous systems. 3.1. Specification model In this approach, we represent systems as a hierarchical network of modules. Each module consists of a behavior ....

G. Nicolescu, S. Yoo, A.A. Jerraya, "Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design", Proc. of Design Automation and Test in Europe, mars, 2001.

....with multiple abstraction levels can give an intermediate system specification that consists of sub systems or components at different abstraction levels. To integrate heterogeneous components within a system, wrappers have been widely used for simulation and synthesis [4] 8] 9] 10] 11] 12] 13][14]. In simulation, for instance, BFM (bus functional model) encapsulates a functional model with a cycle accurate interface [10] 11] BCASH (bus cycle accurate shell) adapts RPC (remote procedural call) and cycle accurate communication [8] 9] In [13] and [14] interfaces of mixed level cosimulation ....

.... and synthesis [4] 8] 9] 10] 11] 12] 13] 14] In simulation, for instance, BFM (bus functional model) encapsulates a functional model with a cycle accurate interface [10] 11] BCASH (bus cycle accurate shell) adapts RPC (remote procedural call) and cycle accurate communication [8] 9] In [13] and [14], interfaces of mixed level cosimulation are presented between protocol fixed communication and cycle accurate communication [13] and protocol neutral and protocol fixed communication [14] In system synthesis, a bus wrapper, a processor template, or a protocol transducer is used to adapt a ....

[Article contains additional citation context not shown here]

G. Nicolescu, S. Yoo, and A. A. Jerraya, "Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design", Proc. Design Automation and Test in Europe, 2001.

No context found.

G. Nicolescu, S. Yoo, and A. A. Jerraya, "Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design", to appear in Proc. Design Automation and Test in Europe, 2001.

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G. Nicolescu, S. Yoo, and A. Jerraya, "Mixed- Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design," Proc. Conf. Design, Automation, and Test in Europe, ACM Press, New York, 2001, pp. 754-759.

No context found.

G. Nicolescu, S. Yoo, A. A. Jerraya, "Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design" , In Proceedings of DATE 2001

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G. Nicolescu, G.; S. Yoo; A. Jerraya. Mixed-level cosimulation for fine gradual refinement of communication in SoC design, Design, Automation and Test in Europe, 2001.

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