A. Nayak, A. C. M. Haldar, and P. Banerjee. Precision and error analysis of matlab applications during automated hardware synthesis for FPGAs. In Design, Automation and Test in Europe Conf., 2001.  Home/Search Document Details and Download
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Optimum Wordlength Allocation - Constantinides, Cheung, Luk (2002) (Correct)
....of the effectiveness of wordlength optimization techniques with respect to optimum solutions. The wordlength optimization techniques of inter est are those which allow a user controlled trade off between implementation area and signal quality at the DSP system outputs, such as those described by [1, 3, 4, 5]. The Mixed Integer Linear Programming (MILP) technique described in this paper has been applied to several small benchmark circuits, and the results com pared to the heuristic presented in [1] Modelling as a MILP permits the use of industrial strength MILP solvers such as BonsaiG [6] Although ....
....the problem addressed in this paper is NP hard. There are, however, several published approaches to wordlength optimization. Those offering an area signal quality tradeoff are all of an heuristic nature [1, 3, 5] or do not support different fractional precision for different internal variables [4]. Bendertl and Perona [8] have proposed an analytic method for wordlength optimization based on interval arithmetic. The authors propose a multi interval approach, and demonstrate that the addition, subtraction, multiplication and division of the proposed intervals result in similar intervals, ....
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A. Nayak, M. Haldar, A. Choudhary, and P. Banerjee, "Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs," in Proc. Design Automation and Test in Europe, Munich, Germany, 2001, pp. 722-728.
Accurate Area and Delay Estimators for FPGAs - Anshuman Nayak And (2002) Self-citation (Nayak Haldar Banerjee) (Correct)
....this information to scalarize the MATLAB AST. The AST is then levelized wherein complex expressions are broken down into simple expressions with at most three operands. A dependency analysis phase infers the control and data dependencies present in the AST. A precision and error analysis phase [21] infers the optimum number of bits required for representing the variables in the MATLAB AST and generates a resource optimized VHDL AST. A memory packing phase [21] packs more than one array element into a single memory location depending on the array precision and optimizes on the number of ....
....A dependency analysis phase infers the control and data dependencies present in the AST. A precision and error analysis phase [21] infers the optimum number of bits required for representing the variables in the MATLAB AST and generates a resource optimized VHDL AST. A memory packing phase [21] packs more than one array element into a single memory location depending on the array precision and optimizes on the number of memory accesses. The parallelization phase [25] extracts fine grain parallelism within a single FPGA based on a prediction of the available FPGA resources. A coarse ....
[Article contains additional citation context not shown here]
A. Nayak, M. Haldar, A. Choudhury and P. Banerjee, Precision And Error Analysis Of MATLAB Applications During Automated Hardware Synthesis for FPGAs, Proc. Design Automation and Test Conference in Europe, DATE 2001, pp. 722-728
Optimized Hardware Synthesis for FPGAs - Haldar (2001) Self-citation (Haldar) (Correct)
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A. Nayak, M. Haldar, A. Choudhary and P. Banerjee, Precision And Error Analysis Of MATLAB Applications During Automated Hardware Synthesis for FPGAs , Design Automation and Test in Europe, March 2001.
Efficient Static Analysis of Fixed-Point Error in DSP.. - Fang, Rutenbar, Chen (Correct)
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A. Nayak, A. C. M. Haldar, and P. Banerjee. Precision and error analysis of matlab applications during automated hardware synthesis for FPGAs. In Design, Automation and Test in Europe Conf., 2001.
Variable Precision Analysis for FPGA Synthesis - Mark Chang And (Correct)
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A. Nayak, M. Haldar, et al., "Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs," in Design Automation & Test, March 2001.
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