Yeh, C.-H., E.A. Varvarigos, and B. Parhami, "Efficient VLSI layouts of hypercubic networks," Proc. Symp. Frontiers of Massively Parallel Computation, Feb. 1999, to appear. Home/Search Document Details and Download
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The Recursive Grid Layout Scheme for VLSI Layout of.. - Yeh, Parhami, Varvarigos (1999) Self-citation (Yeh Varvarigos) (Correct)
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Yeh, C.-H., E.A. Varvarigos, and B. Parhami, "Efficient VLSI layouts of hypercubic networks," Proc. Symp. Frontiers of Massively Parallel Computation, Feb. 1999, to appear.
VLSI Layout and Packaging of Butterfly Networks - Yeh, Parhami, Varvarigos, Lee (2000) (1 citation) Self-citation (Yeh Varvarigos) (Correct)
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Yeh, C.-H., E.A. Varvarigos, and B. Parhami, "Efficient VLSI layouts of hypercubic networks," Proc. Symp. Frontiers of Massively Parallel Computation,Feb. 1999, pp. 98-105.
On the VLSI Area and Bisection Width of Star Graphs and.. - Yeh, Parhami Self-citation (Yeh) (Correct)
.... be laid out at least as effi ciently as the comparable n cubes This question was partially answered by Sykora and Vrt o [22] who provided a layout for an N node star graph that has an area of 4:5N 2 , which is within a constant factor from the 0: 4N 2 area of a similar size hypercube [27, 28]. However, its leading constant is larger than that of the hypercube layout area by a factor of 10.125. Moreover, the lower bound given in [22] for the area of the star graph is smaller than that of a similar size hypercube [27, 28] by a factor of 348: 4. Therefore, although the proofs in [22] ....
....factor from the 0: 4N 2 area of a similar size hypercube [27, 28] However, its leading constant is larger than that of the hypercube layout area by a factor of 10.125. Moreover, the lower bound given in [22] for the area of the star graph is smaller than that of a similar size hypercube [27, 28] by a factor of 348: 4. Therefore, although the proofs in [22] show that the layout area of a star graph is within a constant factor from that of a similar size hypercube, and the layout area of an n star is asymptotically larger than that of an n cube, the following questions remained ....
[Article contains additional citation context not shown here]
Yeh, C.-H., E.A. Varvarigos, and B. Parhami, " Effi cient VLSI layouts of hypercubic networks," Proc. Symp. Frontiers of Massively Parallel Computation, Feb. 1999, pp. 98105.
Multilayer VLSI Layout for Interconnection Networks - Yeh, Varvarigos, Parhami (2000) Self-citation (Yeh Varvarigos) (Correct)
....The layout of interconnection networks has important cost and performance implications for single chip multiprocessors and parallel distributed systems based on such components. Thus, there is currently renewed interest in fi nding effi cient VLSI layouts for various interconnection networks [3, 8, 10, 12, 13, 21, 28, 30, 31, 32, 35]. VLSI layout of interconnection networks is usually derived under the Thompson model, where two layers of wires are assumed. However, the assumption of two wiring layers cease to be realistic as more and more layers of wires become available in VLSI chips at reasonable cost. When the numbers of ....
....N ) Let us now consider a k ary n cube cluster c [4] as an example of PN clusters. Assume that the clusters in the k ary n cube cluster c are c node hypercubes. Then a block with area O(c 2 =L 2 ) is suffi cient to accommodate the c node cluster and its inter cluster links (see Section 5or [31]) Since these blocks are arranged as a k n=2 Theta k n=2 grid, the increase in area is negligible as long as the number c of nodes in a cluster is not very large; that is, c = o(k n=2 Gamma1 ) so that k n=2 c L = o( k n L(k Gamma1) or o( k n Gamma1 L ) when k is not a ....
[Article contains additional citation context not shown here]
Yeh, C.-H., E.A. Varvarigos, and B. Parhami, " Effi cient VLSI layouts of hypercubic networks," Proc. Symp. Frontiers of Massively Parallel Computation, Feb. 1999, pp. 98105.
VLSI Layout and Packaging of Butterfly Networks - Yeh, Parhami, al. (2000) (1 citation) Self-citation (Yeh) (Correct)
....performance achieved by lowering various performance hindrances, such as signal propagation delay, drive power, and fraction of data transfers to off chip destinations. This explains the reintensified research on finding efficient VLSI layouts and packaging, especially for butterfly networks [1, 10, 11, 16, 21, 26, 27]. Efficient layouts and packaging considerations for other interconnection networks can be found in [7, 8, 12, 13, 24] Butterfly networks are among the most important topologies for building commercial and experimental parallel computers, special purpose processors, and network switches. ....
....under the grid model, showing that an N node butterfly network can be laid out in N 2 log 2 2 N o i N 2 log 2 N j area using two layers of wires. They also showed that the layout area is optimal within a factor of 1 o(1) when area is defined by an upright encompassing rectangle. In [26, 27], we proposed optimal VLSI layouts for butterfly networks (in asymptotically the same area as in [1] based on optimal 2 D layouts of complete graphs. In our layout, the network nodes (and clusters of nodes) are aligned as a 2 D grid so that they utilize area efficiently, especially when network ....
[Article contains additional citation context not shown here]
Yeh, C.-H., E.A. Varvarigos, and B. Parhami, "Efficient VLSI layouts of hypercubic networks," Proc. Symp. Frontiers of Massively Parallel Computation, Feb. 1999, pp. 98-105.
Layout Area of the Hypercube - Even, Kupershtok (2003) (Correct)
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C.H. Yeh, E.A. Varvarigos and B. Parhami, "Efficient VLSI Layout of Hypercubic Networks", Proc. Symp. Frontiers of Massively Parallel Computation, Feb. 1999, pp.98-105.
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