R.L. Geiger, P.E. Allen, N.R. Strader, "VLSI Design Techniques for Analog and Digital Circuits", McGraw-Hill, 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....easily added. Index Terms Analog MOS integrated circuits, design parameters, parametric analyses, software tools for education. INTRODUCTION The usual methodology for teaching analog integrated circuit design consists of sequentially introducing to the student four different groups of concepts [1][2] 3] Concepts related to the operation of the devices that are used in analog circuits. Concepts related to the structure and operation of the basic building blocks of analog circuits (e.g. current sources, single stage amplifiers, active loads, etc. Concepts related to the ....

Geiger, R.L., Allen, P.E., Strader, N.R. VLSI Design Techniques for Analog and Digital Circuits. McGraw-Hill, 1990.

....being implemented. H z b z a z m m m M n n n N ( 0 0 (1) The chosen structure also allows the possibility of following up errors due to coefficients quantization. In order to implement adders and multipliers in this structure, classical structures were chosen [3] 5] [6]. 8 bits multipliers and 16 bits adders perform the calculations using fixedpoint arithmetic [2] The data imput and output are 8 bits digital ports. An analog data output is also provided through the R 2R DAC ladder implemented with transistors [4] The structure was designed to work with audio ....

R.L.Geiger, P.E.Allen and N.R.Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill, Inc, 1990.

.... mixed signal analogue digital system, typically consists of an Analogue to Digital Converter (ADC) a digital circuit and a Digital to Analogue Converter (DAC) The interfacing to the analogue word is done through the two converters, while the desired algorithm is performed by the digital circuit [42,45,46]. Input level shifting, analogue sampling and antialiasing filtering might be needed at the input, while some smoothing must be performed at the output. In general the ADC will convert a sampled analogue signal to a digital word representation. Often more than one analogue inputs are multiplexed ....

....in figure 2 13. During the phase Phi 1 of the non overlapping clocks ( Phi 1 ; Phi 2 ) the capacitor C is charged to Q in = CV 1 . During Phi 2 the charge which is flowing at the output is Q out = GammaC V 2 . Therefore the flow of the charge is given by the equation Q = C(V 1 Gamma V 2 ) [50,44,46]. If this event takes place f s times per second the current which flows through the capacitor is I SC = f s (V 1 Gamma V 2 ) R eq = V 1 Gamma V 2 I SC = 1 f s C SC is a well established respectable technique, much used by industry. Since the first practical implementation of SC ....

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N. S. R.L. Geiger, P.E. Allen, VLSI design techniques for analog and digital circuits. McGraw-Hill, 1990.

....and allows lectures to be tailored to meet individual needs. Students are required to buy a text book, but are allowed the flexibility of choosing one that would be most helpful to them. To fit their backgrounds, interests, and projects, students have chosen texts emphasizing digital [5] or analog [6] circuits, technology [7] architecture [8] and circuit compilers [9] Since a student s greatest gains in competence and confidence come through actually doing mi4 crosystem design, the course is oriented almost entirely toward the projects. Students can choose whether to work in small groups ....

Randall L. Geiger, Phillip E. Allen, and Noel R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill, 1990.

....guidelines for the optimum application of the MRC. Key Words: RC active circuits, MOSFET C circuits, MOS resistive circuit, double MOSFET, four transistor transconductor 1. The MOS Resistive Circuit The MOS Resistive Circuit (MRC) firstly proposed in [1] and also reported as Double MOSFET in [2,3], is a four transistor based cell, shown in Fig. 1(a) that has become very popular for the integrated implementation of continuous time circuits, particularly those originated from classical RC active prototypes using operational amplifiers [1,4,5] The cell is nothing but a transconductor ....

Geiger, R. L., Allen, P. L. and Strader, N. R., VLSI Design Techniques for Analog and Digital Circuits. McGraw Hill Publishing Company, ISBN 0-07-023253-9, 1990.

....constitutes at least half of the design cycle in VLSI design. As VLSI designs become larger, their simulation becomes more time consuming. Circuit simulations can be classified into four groups: analog simulation, switch level simulation, gate level simulation, and function level simulation [18, 37]. Only gate level simulation is considered in this work where a circuit contains a set of logic gates such as NOT, AND, OR, NAND, NOR gates, and flip flops. Gate level logic simulation is a primary tool in VLSI circuit design to verify if the design of a circuit is correct and to analyze the ....

....problems are also described in that chapter. 7 Chapter 2 Background 2.1 VLSI Circuit Simulation VLSI circuit simulation is normally used to verify the functional correctness and timing of a circuit design. Depending on the level of detail, circuit simulation can be classified as follows [86, 18, 37]: ffl Behavioral or functional simulation : A designer describes the behavior of components of a circuit design at a high level. Simulation is performed based on these high level components. The high level functions indicate transformations on data as the data move from one storage device to ....

R. L. Geiger, P. E. Allen, and N. R. Strader, "VLSI Design Techniques for Analog and Digital Circuits," McGraw-Hill, pp. 909-917, 1990.

.... a time; 2) communication resources are shared by many cells; 3) global processor and local processors infer the input operand intensity by measuring the time an event is received [e.g. Traditionally, the intensity to time relationship has been used in single and double slope A D converters [10]. In vision, it has been used to improve diffusion based image segmentation [7] a local operation, and for image acquisition in a SIMD architecture [9] an architecture well suited only for local operations. In contrast, our architecture allows global operations and shares some features of ....

R. I. Geiger, L. P. E. Allen, and N. R. Strader, VLSI Design Techniques for Analog and Digital Circuits. New York: McGraw-Hill, 1990.

....adder design presented in the following is done on a symbolic design level. The lengths of the wires cannot be estimated in general, since they largely depend on the technology used. For some design processes this simplifying assumption is realistic, i.e. channelless gate arrays or sea of gates [32], 33] As in [5] 4] the areatime optimal adder design itself is formulated as a dynamic programming problem. We present two methods for this first phase. The first one was presented in [34] and is based on a straightforward dynamic program. However, this algorithm is impracticable for large ....

....the cell area, i.e, we do not take the interconnect area into account. The lengths of the wires cannot be estimated in general, since they largely depend on the technology used. For some design processes this simplifying assumption is realistic , i.e. channelless gate arrays or sea of gates [33] [32]. Note once more that the wire length can easily be approximated if the physical design is done along the lines of the symbolic design. B. Formulation as dynamic programming problem The problem can be described as follows: Given the number n of bits and the delay t n (e.g. measured in units of ....

R.L. Geiger, P.E. Allen, and N.R. Strader, VLSI-Design Techniques for Analog and Digital Circuits, McGraw Hill International Editors, 1990.

....All storage elements can be implemented using the VLSI design style proposed in [20] Transmission gates can be used to implement the demultiplexer, multiplexer and decoder circuits. The rest of the control logic can be implemented using regular static CMOS gates with optimized transistor sizes [36]. The global clock needs a specialized tree like network to drive all necessary gates and special care must be taken in order to minimize the effects of clock skew on system performance. ....

Randall Geiger, Phillip E. Allen, and Noel R. Strader. VLSI design techniques for Analog and Digital circuits. Electrical engineering. McGraw-Hill, 1990. 44

....on a SUN Sparc 5 workstation. The five examples are: ladder7 an RC ladder with 7 stages [10] ladder21 an RC ladder with 21 stages [10] filter4 a 4th order low pass filter network [11] 4] filter8 an 8th order band pass filter [11] and cascode op amp the small signal model for a cascode op amp [2] for which we manually built a hierarchical description. The results of our experiments are summarized in Table 1.2. Columns 2 and 3 indicate the sizes of the analyzed systems (circuits) in terms of their 12 Example # of un # of sym Required memory Function sharings knowns bols # of nodes # ....

R. Geiger, P. Allen, N. Strader, "VLSI Design Techniques for Analog and Digital Circuits", McGraw-Hill, 1990.

...., together with fst X;Y ; sndX;Y and uX for each pair of objects X and Y , subject to the equivalence e = f if e and f are equal under the equivalence generated by the equivalence of Tables 1 and 2. 2 4 Nets Net lists are a model of circuit connectivity, and are used in circuit extraction [4] and simulation [5] A net list consists of ffl a list of elements, a list of wires, a list of input wires and a list of output wires, ffl an assignment of components to elements, and sorts to wires, ffl connectivity information saying which wires are connected to which elements, and ffl ....

Randall L. Geiger, Phillip E. Allen, and Noel R. Strader. VLSI Design Techniques for Analog and Digital Circuits. McGraw Hill, 1990.

....in the sense that equivalent pictures represent equal relations. Pictures are an excellent aid to reasoning but they are unwieldy and difficult to automate: we therefore introduce networks of wires and basic components. Networks abstract from the net list model of circuit connectivity [6, 13] by ignoring the size and position of components in a circuit. In the absence of empty types, the allegory of networks and network homomorphisms is equivalent to the allegory of pictures and picture homomorphisms. Further, we prove soundness: two pictures P and P 0 denote the same relation ....

....cell. Definition 3 A network of type A B is a triple (N; l; r) where N is a finite set of nodes, and l : A and r : B are names. We call l and r the input and output names of the network respectively. Networks generalise the net list model of circuit connectivity, used in circuit extraction [6] and simulation [13] A net list is a network together with geometric information about the size and position of each instance of a cell. Remark 4 We do not distinguish between ff equivalent networks (networks which are equal up to a type preserving bijection on basic names) Definition 5 Let ....

Randall L. Geiger and Phillip E. Allen and Noel R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw Hill, 1990.

....logic values can be generated by increasing the width of the transistor by a factor equal to the ratio of the desired current and the basic current. An alternative way to produce a current source is to use the depletion mode MOS transistors. Also, often a resistor and the current mirror are used [42] to obtain a current source. Signal distribution can be performed using current mirrors, which can be of either Ntype or P type. We will use both types. The current produced at the output is determined by the input current and the ratio between the output and input W L values (scale factor) In ....

....containing the binary code for the amount of input current are generated. 13 2.3 Current Mirrors The central building block in current mode CMOS circuits is the current mirror. The characteristics of this circuit will be described shortly. Books by Wang [119] and Geiger, Allen and Strader [42] contain detailed description and derivations of formulae related to this discussion. MOS current mirrors can come in various configurations. The mirror shown in Figure 2.1 is usually called a simple mirror. Some of the other configurations are: Wilson current mirror, cascode current mirror and ....

Geiger. R. L., Allen, P. E. and Strader, N. R., VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill, 1990.

....Approximation Register TTL Transistor Transistor Logic UV Ultra Violet VLSI Very Large Scale Integration WSI Wafer Scale Integration Page xiv Symbols A list of the less commonly used symbols appearing in the thesis is given here. For standard symbols refer to the literature (e.g. Geiger et al. [77], Hertz et al. 95] or S anchez Sinencio and Lau [206] As index: index runs over all possible values. Omega Vector multiplication by coordinates ( Omega i = 1 i 1 ; 2 i 2 ; T ) Convolution operator. b As Superscript: i b : bit number of i. B Number of bits; B is ....

.... high resolution synapse strengths are needed, digital memories consume more area than simple analogue memories: The size of a digital memory scale as O(log w res ) whereas analogue scale as O(w res ) where w res is the resolution of the synapse strength (limited by noise; cf. e.g. Geiger et al. [77]) For typical ANN system which require a weight resolution of 8 16 bit, the analogue solution is usually the smallest by far. Chapter 2.2.3 Implementation of the neural network Page 19 The most severe problem with embedding digital circuitry in an analogue system is the need for data ....

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Randall L. Geiger, Phillip E. Allen and Noel R. Strader, VLSI Design Techniques for Analog and Digital Circuits, Singapore: McGraw-Hill Publishing Company, 1990.

....component values from a set preferred of values. For the design of Integrated Circuits it can also be desirable to use a standard set of passive component values. For example, to obtain accurate ratio matching of integrated resistors and capacitors by stacking identical unit valued components [1]. The usual design approaches produce circuits in which the permitted component values are assumed to be unrestricted. The circuit is then converted to a practical circuit by simple rounding of the exact component values to the nearest value in the permitted set. Of course, in general the circuit ....

Geiger, R.L., Allen, P.E. and Strader, N.R.: VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill, New York, 1990, pp 79-82.

....the circuit topologies of the Basic Two Stage (BTS) op.amp. the Output Transconductance Amplifier (OTA) and the Folded Cascode OTA (FCO) For these topologies, analytic design equations can be derived by means of first order circuit analysis techniques and topology specific approximations [20] [21]. These analytical expressions can be used for approximate analysis of circuit performances, 4] 8] 10] 11] 14] However, the results obtained with these approximate expressions can differ from the actual cell performances, due to a number of reasons: ffl Approximate expressions usually ....

R.L.Geiger, P.E.Allen and N.R.Strader. VLSI design techniques for analog and digital circuits. McGraw--Hill,

....used correspond to a MOSIS 0:8 CMOS process. With decreasing VLSI feature size, open faults in the interconnect (i.e. discontinuities in wires) tend to occur due to manufacturing defects and electro migration, with both these problems becoming increasingly acute in the submicron regimes [11] [15] Previous routing techniques do not address this issue of the reliability of the routing, i.e. the ability of the interconnect to tolerate open faults. In contrast, our nontree routing techniques can tolerate an open fault along the majority of the wires. Another benefit of non tree ....

R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill, New York, 1990.

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R.L. Geiger, P.E. Allen, N.R. Strader, "VLSI Design Techniques for Analog and Digital Circuits", McGraw-Hill, 1990.

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Geiger, R., Allen, P., and Strader, N., VLSI: Design Techniques for Analog and Digital Circuits, McGraw- Hill, New York, NY (1990).

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R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI design techniques for analog and digital circuits. New York: McGraw-Hill, 1990.

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Geiger, R., Allen, P., and Strader, N., VLSI: Design Techniques for Analog and Digital Circuits, McGraw- Hill, New York, NY (1990).

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R. Geiger, P. Allen, and N. Stroder, VLSI design techniques for analog and digital circuits (McGraw Hill, New York, 1990), pp. 590-593.

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