K. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken, "An asynchronous instruction length decoder," presented at the 5th Int. Symp. Advanced Research in Asynchronous Circuits and Systems, Apr. 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

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K. Stevens, S. Rotem, R. Ginosar, P. A. Beerel, C. J. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken, An asynchronous instruction length decoder. In IEEE Journal of Solid State Circuits, 36(2): 217-228, Feb. 2001.

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K. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken. An Asynchronous Instruction Length Decoder. IEEE Journal of Solid State Circuits, 36(2):217--228, Feb. 2001.

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K. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken. An asynchronous instruction length decoder. IEEE Journal of Solid-State Circuits, 35(2):217-228, February 2001.

....test chip, and may be formalized and automated. Index Terms Asynchronous design, dynamic logic circuit, high performance, low power design, performance tradeoffs. I. INTRODUCTION T HE design of RAPPID, the asynchronous instruction length decoder, took more than two years to complete [1]. The primary goal was to investigate whether asynchronous design could improve performance in high end microprocessors. This naturally led to the effort, reported in this paper, to study and develop circuits, computer aided design (CAD) and methodology most suitable for aggressive timed ....

....timing had a significant impact on the RAPPID results. The timed asynchronous circuits, when compared to similar clocked logic in a commercial synchronous implementation, showed a 3 improvement in throughput, a 2 improvement in latency, and half the energy per operation, at a 20 area penalty [1]. Although harder to quantify, we feel that relative timing was also key in achieving the 95 stuck at testability in RAPPID with our functional built in self test method through removing redundancies that naturally result through fixed signal orderings induced by timing. Most of the RT circuits ....

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K. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken, "An asynchronous instruction length decoder," IEEE J. Solid-State Circuits, vol. 36, pp. 217--228, Feb. 2001.

.... increase performance, circuit designers are experimenting with timed circuits a class of circuits that rely on a complex set of timing constraints for correct functionality [1, 2] This is evidenced by industrial scale experimental designs such as the Intel RAPPID instruction length decoder [3], SUN s GASP pipelines [4] IBM s IPCMOS pipelines [5] the IBM guTS microprocessor [6] and the University of Washington output prediction logic (OPL) 64 bit adder [7] Although RAPPID, GASP, and IPCMOS are asynchronous and guTS and OPL are synchronous, all of these designs use formal timing ....

....called zones. Let x and y be variables and q be a constant rational number, then x y q relates the di#erence between x and y to q. An example of a zone from the net fragment shown in Fig.1 is: 7, 2 5 . This zone restricts the separation between xA and xB to the range [3, 7] and the separation between xA and xC to the range [2, 5] Any separations that are not defined in the zone are unbounded. If xA , xB , and xC correspond to the transitions in Fig.1, then the example zone I defines when B and C can occur in time relative to transition A. If I is a set of defined ....

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K. S. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. J. Myers, K. Y. Yun, R. Koi, C. Dike, and M. Roncken. An asynchronous instruction length decoder. IEEE Journal of Solid-State Circuits, 36(2):217--228, February 2001.

....to wire delays. The synthesis techniques described in this paper are an attempt to combine the expressive power of Signal Transition Graphs (that allow a designer to finely tune concurrency, sequencing and choice) with the optimization power of Burst Mode FSMs and manual timing driven design [12] (that allow a designer to avoid waiting for signals that are known to be stable) By doing so, high optimization levels are achieved, while keeping the flexibility of our CAD framework. Of course, this power comes at a price: our synthesis algorithms are radically more complex than their ....

....will always fire before event d. Lazy transition systems are used as the computational model for synthesis. C. Synthesis flow The synthesis flow proposed in this paper follows the paradigm assume and, if useful, guarantee . Similar principles have been used in recent asynchronous designs [12], 22] 23] 24] Given an untimed computational model, e.g. a transition system, synthesis of an asynchronous circuit is performed as follows: 1. Derive a set T of timing assumptions on the behavior of the system. 2. Synthesize the circuit by using a subset T T of useful timing ....

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Kenneth S. Stevens, Shai Rotem, Ran Ginosar, Peter Beerel, Chris J. Myers, Kenneth Y. Yun, Rakefet Kol, Charles Dike, and Marly Roncken, "An asynchronous instruction length decoder," IEEE Journal of Solid-State Circuits, vol. 36, no. 2, pp. 217--228, Feb. 2001.

....Projects. Email: eemercer ece.utah.edu Email: myers ece.utah.edu Email: yoneda cs.titech.ac.jp Email: haoz us.ibm.com #2002 Published by Elsevier Science B. V. 1 Introduction In order to achieve high performance, designers are experimenting with aggressive timed circuits [26,27,24,12]. Designing these circuits, however, in a fully manual style is very di#cult; thus, CAD tools are essential for synthesis and verification. An important issue in developing such CAD tools is the avoidance of state explosion. This paper presents two approaches to managing state explosion: first, a ....

Stevens, K. S., S. Rotem, R. Ginosar, P. Beerel, C. J. Myers, K. Y. Yun, R. Koi, C. Dike, and M. Roncken, An asynchronous instruction length decoder, IEEE Journal of Solid-State Circuits 36 (2001), 217--228.

....in gates but may be sensitive to wire delays. The synthesis techniques described in this paper are an attempt to combine the expressive power of STGs (that allow a designer to finely tune concurrency, sequencing and choice) with the optimization power of BM FSMs and manual timing driven design [12] (that allow a designer to avoid waiting for signals that are known to be stable) By doing so, high optimization levels are achieved, while keeping the flexibility of our CAD framework. Of course, this power comes at a price: our synthesis algorithms are radically more complex than their BM ....

....event will always fire before event . Lazy transition systems are used as the computational model for synthesis. C. Synthesis Flow The synthesis flow proposed in this paper follows the paradigm assume and, if useful, guarantee. Similar principles have been used in recent asynchronous designs [12], 22] 24] Given an untimed computational model, e.g. a transition system, synthesis of an asynchronous circuit is performed as follows. 1) Derive a set of timing assumptions on the behavior of the system. 2) Synthesize the circuit by using a subset of useful timing assumptions. 3) Derive a ....

[Article contains additional citation context not shown here]

K. S. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. J. Myers, K. Y. Yun, R. Kol, C. Dike, and M. Roncken, "An asynchronous instruction length decoder," IEEE J. Solid-State Circuits, vol. 36, pp. 217--228, Feb. 2001.

....as simply as in the untimed cases, because some timed events cannot occur after a certain time point due to the timing constraints on the transitions. Thus, 1 In order to define 2j precisely, we may consider an auxiliary transition aux which never becomes enabled. 3 u [1,100] [4,5] M w I= u O= w M I= w O= u 1 2 u [3,10] 3,10] w Figure 1. Example 1. u [1,5] 1,5] M w I= w O= u M I= u O= w 1 2 w [1,10] 1,10] u Figure 2. Example 2. before classifying overstepped timed traces, we intuitively discuss when failures should and should not occur. We ....

....q # y M has an output . Thus, for P , either # : or # 2: is not in , 0,5] M w I= w O= M I= O= w 1 2 w [1,1] u [1,1] 0,5] M w I= w O= u M I= u O= w 1 2 w [1,1] 0,5] u (a) b) Figure 3. Example 3. 0,5] M w I= w O= M I= O= w 1 2 w [4,10] Figure 4. Example 4. and for j , either # 2: or # 2: is not in . From this, the overstepped timed traces of k and cannot be in the failure set of h k j c f h M . The non overstepped timed traces cannot be, either. Hence, we can conclude that h B u c f ....

K. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken. An asynchronous instruction length decoder. IEEE Journal of Solid-State Circuits, 35(2):217--228, February 2001.

....TL(y; N) without firing any transitions. It is under the control of N . Thus, we should consider that the overstepped timed traces are not in P . On the other hand, if every wire in limit(y; N) is an input, N can only wait for the other modules to produce the expected outputs. In other u [1,100] [4,5] M w I= u O= w M I= w O= u 1 2 u [3,10] 3,10] w Figure 1. Example 1. u [1,5] 1,5] M w I= w O= u M I= u O= w 1 2 w [1,10] 1,10] u Figure 2. Example 2. words, if no outputs are produced, the only action that N can do is to fail. Thus, it is natural to consider that ....

....virtual output of M 2 and the disabled virtual input of M 1 . Then, according to the [0,5] M w I= w O= M I= O= w 1 2 w [1,1] u [1,1] 0,5] M w I= w O= u M I= u O= w 1 2 w [1,1] 0,5] u (a) b) Figure 3. Example 3. 0,5] M w I= w O= M I= O= w 1 2 w [4,10] Figure 4. Example 4. above criteria, we have (v 1 ; 2 F 1 with 5 because this is overstepped, and we have (v 1 ; 2 F 2 because this is neither overstepped nor in trace(N 2 ) In Figure 4, limit( N 1 ) includes only an input, while limit( N 2 ) has an output. Thus, we have (w; ....

K. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken. An asynchronous instruction length decoder. IEEE Journal of Solid-State Circuits, 35(2):217--228, February 2001.

No context found.

K. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, and M. Roncken, "An asynchronous instruction length decoder," presented at the 5th Int. Symp. Advanced Research in Asynchronous Circuits and Systems, Apr. 1999.

No context found.

K. S. Stevens, S. Rotem, R. Ginosar, P. A. Beerel, C. J. Myers, K. Y. Yun, R. Koi, C. Dike, and M. Roncken, "An asynchronous instruction length decoder," IEEE Journal of Solid-State Circuits, vol. 36, pp. 217--228, Feb. 2001.

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