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HotLeakage: A Temperature-Aware Model of.. - Zhang, Parikh.. (2003) (6 citations) (Correct)
....Technology Roadmap for Semiconductors (ITRS) 24] predicts that in the next several processor generations, leakage may constitute as much as 50 of total power dissipation. Recently, a great deal of research work in the architecture community has focused on reducing leakage power in the caches [11, 13, 14, 18, 22, 27, 28], branch predictor [15, 16] register file [2] issue queues [12, 21, 8, 9] and the ALUs [10] Leakage control at the architecture level is attractive, because architectural techniques can control large groups of circuits (e.g. cache lines, banks, or the entire cache) at once. Yet most of these ....
....accordingly. The mean of those leakage currents is used in the following simulations in order to show the effects of the parameter variations. 3 Using HotLeakage The HotLeakage simulation tool is currently based on Wattch [5] and also uses some code from the Princeton Agere cache decay [18] simulator. It implements various cache leakage control techniques in cache.c, cache leak ctrl.c and sim outorder.c, with calls to the suitable routines within HotLeakage (leakage.c and leakinit.c) Using this system as a starting point, the simulator can be extended easily to model new ....
[Article contains additional citation context not shown here]
S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proceedings of the 28th Annual International Symposium on Computer Architecture, July 2001.
HotLeakage: A Temperature-Aware Model of.. - Zhang, Parikh.. (2003) (6 citations) (Correct)
....Technology Roadmap for Semiconductors (ITRS) 24] predicts that in the next several processor generations, leakage may constitute as much as 50 of total power dissipation. Recently, a great deal of research work in the architecture community has focused on reducing leakage power in the caches [11, 13, 14, 18, 22, 27, 28], branch predictor [15, 16] register file [2] issue queues [12, 21, 8, 9] and the ALUs [10] Leakage control at the architecture level is attractive, because architectural techniques can control large groups of circuits (e.g. cache lines, banks, or the entire cache) at once. Yet most of these ....
....accordingly. The mean of those leakage currents is used in the following simulations in order to show the effects of the parameter variations. 3 Using HotLeakage The HotLeakage simulation tool is currently based on Wattch [5] and also uses some code from the Princeton Agere cache decay [18] simulator. It implements various cache leakage control techniques in cache.c, cache leak ctrl.c and sim outorder.c, with calls to the suitable routines within HotLeakage (leakage.c and leakinit.c) Using this system as a starting point, the simulator can be extended easily to model new ....
[Article contains additional citation context not shown here]
S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proceedings of the 28th Annual International Symposium on Computer Architecture, July 2001.
Tuning Garbage Collection in an Embedded Java Environment - Chen, Shetty, Kandemir, .. (2002) (3 citations) (Correct)
.... [8] However, leakage energy consumption is becoming an equally important portion as supply voltages and thus threshold voltages and gate oxide thicknesses continue to become smaller [4] Researchers have started to investigate architectural support for reducing leakage in cache architectures [23, 16]. In this paper, we show that it is possible to also reduce leakage energy in memory by shutting down idle banks using an integrated hardware software strategy. The garbage collector (GC) 13] is an important part of the JVM and is responsible for automatic reclamation of heapallocated storage ....
....architecture and tunes garbage collector for energy optimization. Finally, numerous papers attempt to optimize energy consumption at the circuit and architectural levels. In particular, the leakage optimization circuit employed here tries to reduce leakage current and is similar to that used in [23, 16]. We employ a design that is a simple enhancement of existing voltage down converters present in current memory designs. Further, the circuit with the differential feedback stage helps to respond to load variations faster during normal operation. 6 Conclusions As battery operated Java enabled ....
S. Kaxiras, Z. Hu, M. Martonosi. Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In Proc. the 28th International Symposium on Computer Architecture, June 2001.
Adaptive Cache Decay using Formal Feedback Control - Velusamy, Sankaranarayanan, .. (2002) (1 citation) (Correct)
....to find the correct runtime metric to control, difficult to find a suitable controller design, and difficult to tune the controller to provide acceptable performance. However, the formal part of Other ways of proving bounds are of course possible, e.g. the competitive algorithms approach in [10]. feedback control is usually not the problem, but rather understanding the system and the right way to abstract it into a control loop. These problems are present regardless of whether any formal control techniques are even being considered. Although the formalism of control theory can be ....
....design of these feedback control systems should start from formal, control theoretic formulations. These formulations are no harder to work with than ad hoc control loops, are often able to simplify the design and tuning process, and make the system easier to analyze. 2 Cache Decay Cache decay [10] the running example throughout this paper is a technique for leakage energy savings that waits for some pre determined time, the decay interval, before concluding that a cache line s data is no longer in use and that the line can be deactivated. In almost all formulations of cache decay, ....
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S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proc. ISCA-28, July 2001.
Reducing Set-Associative Cache Energy via.. - Powell, Agarwal.. (2001) (17 citations) (Correct)
....not applicable. Moreover, when working sets do not fit, filtering increases the critical path access time for accessing cached information and may significantly reduce performance. To reduce leakage energy dissipation, Powell, et al. 19] propose a dynamically resizing i cache, and Kaxiras et al. [14] propose using cache decay. These papers do not address dynamic energy, but only leakage energy. 6Conclusions Set associative caches minimize access time by accessing all the data ways in parallel with the tag lookup, although the output of only the matching way is used. The energy spent ....
S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce leakage power. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA), July 2001.
Optimizing the Thermal Behavior of Subarrayed Data Caches - John, Hu, Ziavras Self-citation (Hu) (Correct)
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S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proc. the Int'l Symposium on Computer Architecture, 2001.
Managing Leakage for Transient Data: Decay and.. - Hu, Juang.. (2002) (2 citations) Self-citation (Kaxiras Hu Martonosi) (Correct)
....a charge stored in a 6T cell will be maintained as long as that cell is connected to the drain and source voltages ( and ) Powell et al. 7] proposed a circuit technique called gated V , which disables a region of the cache by disconnecting it from . Kaxiras et al. [6] and Zhou et al. 12] describe architectural policies to guide gated V : individual cache lines which have not been used for a long time should be shut off because they tend to contain data that is not likely to be used again before replacement. These techniques use counters to gauge how long ....
....6T 4T COM2 4T COM3 4T COM4 Figure 5: Normalized leakage energy for branch predictors with standard (Left) and slow decay (Right) 4T cells. Finally, the normal dynamic energy overhead of additional mispredictions must be included in our results. Using a calculation similar to that found in [6], we can evaluate the impact of additional dynamic overhead caused by decayed (and possibly mispredicted) reads. Note that this number is an energy calculation for the entire processor; that is, the dynamic overhead is the extra energy expended by the whole processor due to a longer runtime. ....
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S. Kaxiras, Z. Hu, and M. Martonosi. Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In Proc. ISCA-28, July 2001.
Fast Speculative Address Generation and Way.. - Nicolaescu.. (Correct)
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S. Kaxiras and et al, "Cache decay: exploiting generational behavior to reduce cache leakage power," in ISCA, 2001.
A Highly Configurable Cache for Low Energy Embedded Systems - Chuanjun Zhang San (Correct)
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KAXIRAS,S.,HU, Z., AND MARTONOSI,M. 2001. Cache decay: Exploiting generational behavior to reduce cache leakage power. In the 28th Annual International Symposium on Computer Architecture.
A Self-Tuning Cache Architecture for - Embedded Systems Chuanjun (Correct)
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KAXIRAS, S., HU, Z., AND MARTONOSI, M. 2001. Cache decay: Exploiting generational behavior to reduce cache leakage power. In 28th Annual International Symposium on Computer Architecture.
Soft Error and Energy Consumption Interactions: A.. - Li, Degalahal.. (2004) (Correct)
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S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: exploiting generational behavior to reduce cache leakage power. In Proc. of the 28th annual International Symposium on Computer Architecture, pages 240--251, 2001.
Static Energy Reduction Techniques in Microprocessor Caches - Heather Hanson Stephen (2001) (11 citations) (Correct)
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S. Kaxiras, Z. Hu and M. Martonosi. Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. To appear in International Symposium on Computer Architecture, 2001.
Managing Leakage Energy in Cache Hierarchies - Li, Kadayif, Tsai.. (2003) (Correct)
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S. Kaxiras, Z. Hu, and M. Martonosi, "Cache decay: exploiting generational behavior to reduce cache leakage power," in Proceedings of the 28th annual international symposium on on Computer architecture (ISCA-28), pp. 240--251, 2001.
On Load Latency in Low-Power Caches - Soontae Kim Vijaykrishnan (Correct)
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S. Kaxiras, Z. Hu and M. Martonosi. Cache decay: Exploiting generational behavior to reduce leakage power. In Proc. International Symposium on Computer Architecture,July 2001.
Power-Aware Compilation Techniques for High Performance Processors - Yang (2004) (Correct)
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Stefanos Kaxiras, Zhigang Hu, and Margaret Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In 108 Architecture, pages 240--251, Goteborg, Sweden, June 30--July 4, 2001. IEEE Computer Society and ACM SIGARCH. Computer Architecture News, 29(2), May 2001.
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S. Kaxiras, Z. Hu, and M. Martonosi, "Cache decay: Exploiting generational behavior to reduce cache leakage power," in the 28th International Symposium on Computer Architecture, (Sweden), June 2001.
Low-Leakage Asymmetric-Cell SRAM (TVLSI) - Azizi (2003) (Correct)
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S. Kaxiras, Z. Hu, and M. Martonosi, "Cache decay exploiting generational behavior to reduce leakage power," in Proc. 27th Int. Computer Architecture Symp., Goteborg, Sweden, July 2001.
Managing Leakage Energy in Cache Hierarchies - Li, Kadayif, Tsai.. (2003) (Correct)
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S. Kaxiras, Z. Hu, and M. Martonosi, "Cache decay: exploiting generational behavior to reduce cache leakage power," in Proceedings of the 28th annual international symposium on on Computer architecture (ISCA-28), pp. 240--251, 2001.
Reducing dTLB Energy Through Dynamic Resizing - Delaluz Kandemir Sivasubramaniam (Correct)
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S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: exploiting generational behavior to reduce cache leakage power. Proceedings of the 28th International Symposium on Computer Architecture, June 2001.
Comparison of State-Preserving vs.. - Parikh, Zhang.. (2003) (Correct)
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S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Computer Architecture, July 2001.
Leakage Current: Moore's Law Meets Static Power - Kim (2003) (3 citations) (Correct)
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S. Kaxiras, Z. Hu, and M. Martonosi, "Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power," Proc. 28th Int'l Symp. Computer Architecture (ISCA 28), IEEE CS Press, 2001, pp. 240-251.
An Access Pattern Based Energy Management Strategy for.. - Avanti Nadgir Mahmut (Correct)
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S. Kaxiras et al.Cache decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In Proc. ISCA, Sweden, June 2001.
Tuning Garbage Collection in an Embedded Java Environment - Chen, Shetty, Kandemir, .. (2002) (3 citations) (Correct)
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S. Kaxiras, Z. Hu, M. Martonosi. Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In Proc. the 28th International Symposium on Computer Architecture, June 2001.
Power Efficient Data Cache Designs - Jaume Abella Antonio (Correct)
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S. Kaxiras, Z. Hu, M. Martonosi, "Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power" in ISCA'01, Gteborg, Sweden, June 2001.
On Load Latency in Low-Power Caches - Kim, Vijaykrishnan, John (2003) (Correct)
No context found.
S. Kaxiras, Z. Hu and M. Martonosi. Cache decay: Exploiting generational behavior to reduce leakage power. In Proc. International Symposium on Computer Architecture,July 2001.
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