S. Trimberger, D. Carberry, A. Johnson, and J. Wong, "A Time-Multiplexed FPGA," Proceedings of the IEEE Workshop on FPGA Custom Computing Machines, pp. 22-28, 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....in performance. There are a few traditional configuration memory styles that can be used with reconfigurable systems, including the Single Context model [Xilinx94, Altera98, Lucent98] the Partial Run time Reconfigurable model (PRTR) Ebeling96, Schmit97, Hauck97] and the Multi Context model [DeHon94, Trimberger97]. For Single Context FPGA shown in Figure 1, the whole array can be viewed as a shift register, and the whole chip area must be reconfigured during each reconfiguration. This means that even if only a small portion of the chip needs to be reconfigured, the whole chip is rewritten. Since many of ....

S. Trimberger, D. Carberry, A. Johnson, J. Wong, "A Time-Multiplexed FPGA", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 22-28, 1997.

.... capabilities of dynamically reconfigurable FPGAs such as [15] In order not to take too much time, presynthesized bit streams are generated at compile time and only these configuration streams are overwritten or simply swapped [4] at run time using techniques such as multi context FPGAs [8, 13]. The idea of reconfigurable hardware may, however, be spun further: In the software world, the first generations of microprocessors made use of the ingenious idea of selfreconfiguring program code stepwise in order to execute larger or more complex programs that would otherwise not fit into the ....

S. Trimberger, D. Carberry, A. Johnson, and J. Wong. A time-multiplexed FPGA. In IEEE Symp. on FPGAs and Custom Computing Machines (FCCM), pages 22--28, Apr. 1997.

....[5] was proposed by Bolotski, et al. which also talked about context swapping within an FPGA. In a later paper, DeHon proposed placing DPGAs on the same die as a normal processor to act as a reconfigurable accelerator [6] Xilinx filed a patent on the multi context programmable device in 1995 [7][8]. The patented device has an architecture similar to the Xilinx XC4000E [1] with multiple configuration planes. The reconfigurable communication processor [9] developed by Chameleon systems, Inc. has a reconfigurable fabric with two configurable planes; one for executing while the other configures ....

S. Trimberger, D. Carberry, A. Johnson and J. Wong, "A Time-Multiplexed FPGA," in Proceedings of IEEE symposium on FPGAs for custom computing machines, April 1997.

....the exact reconfiguration time, we have performed a set of simulations with varying reconfiguration times and frequencies with the upper bound of 3 ms for the reconfiguration time. In addition, the reconfiguration time can significantly be improved for the specific design. Context switching FPGAs [15, 18] can be efficiently employed for the accelerator design, where each context corresponds to different configuration for the accelerator. However, such techniques are out of the scope of this paper and will not be discussed in detail. Figure 15 summarizes the results. It gives the relative ....

Trimberger, S., D. Carberry, A. Johnson, and J.A. Wong. Time-Multiplexed FPGA. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines', April 1997, Napa/CA.

....configuration memory replicated in order to contain several configurations for the raw hardware. That is, a multiple context FPGA contains an on chip cache of raw hardware configurations, which are referred to as contexts. Such a cache allows a context switch to occur on the order of nanoseconds [9]. However, loading a new configuration from off chip is still limited by low off chip bandwidth. In the sequel, we will assume a multiple context FPGA which has the architecture of the raw hardware identical with that of an ACEX 1K device from Altera [8] Our choice could allow future single chip ....

Trimberger, S., D. Carberry, A. Johnson, and J. Wong, "A Time-Multiplexed FPGA," in IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, 1997, pp. 22--28.

.... RS INITC RICRS RS RS Idle (RS:Restructuring;INIT:Initialization;C:C om putation;RI:Reinitializing) Figure 7: Time duplexing Reconfigurable computing in FPGAs provides a way to increase the device capacity and improve flexibility when solving a range of problems without duplicating hardware ([15], 16] In the readback signal generator, two dimensions of reconfigurations are considered: reinitializing and restructuring. They are accomplished jointly through hardware and software. 3.4.1 Reinitializing When a read head moves from one track to another, the pulse shape, noise statistics, ....

S. Trimberger, D. Carberry, and A. Johnson, "A time-multiplexed FPGA", Proceedings of The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp.22-8, 1997.

....configuration memory replicated in order to contain several configurations for the raw hardware. That is, a multiple context FPGA contains an on chip cache of raw hardware configurations, which are referred to as contexts. Such a cache allows a context switch to occur on the order of nanoseconds [16]. However, loading a new configuration from off chip is still limited by low off chip bandwidth. In the sequel, we will assume that the architecture of the raw hardware is identical with that of an ACEX 1K device from Altera [17] Our choice could allow future singlechip integration, since ....

....cycles, and a 2 D IDCT can be computed in 56 cycles in the pure software approach. In the FPGA based approach, a DCT coefficient is decoded in 11 cycles, and the 2 D IDCT is carried out with the throughput of 1 32 IDCT cycle. Based on the published work in the field of multiplecontext FPGAs [16], we make a safe assumption and consider that the context switching penality is 10 cycles. 8.1 Pel reconstruction performance evaluation A program which is MPEG compliant has been written in C, compiled and scheduled with TriMedia development tools. The performance evaluation has been done ....

Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A Time-Multiplexed FPGA. In: IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, (1997) 22--28.

....to reconfigure the design. By utilising partial reconfiguration we can reduce n r [8] and hence reduce the total impact reconfiguration has on R. n r may also be reduced through improvements in technology and architectures that support fast reconfiguration through caches or context switches [10]. 5 Generation of Custom Instruction Compared to direct hardware implementations, instruction processors have the added overhead of instruction fetch and decode [7] VL. and EPIC architectures are attempts to reduce the ratio of fetches to execution. Customising instructions is also a technique ....

S. Trimberger, D. Carberry and A. Johnson. A time-multiplexed FPGA. In Proc. FCCM. IEEE Computer Society Press, 1997.

....that a context be fully reprogrammed to perform any modification. This systems does allow for the background loading of a context, where one plane is active and in execution while an inactive place is in the process of being programmed. Figure 15 shows a multi context memory bit, as used in [Trimberger97b]. A commercial product that uses this technique is the CS2000 RCP series from Chameleon, Inc [Chameleon00] This device provides two separate planes of programming information. At any given time, one of these planes is controlling current execution on the reconfigurable fabric, and the other plane ....

....planes is controlling current execution on the reconfigurable fabric, and the other plane is available for background loading of the next needed configuration. P0 P1 P2 P3 Latch active configuration bit C0 C1 C2 C3 configuration data Figure 15: A four bit multi contexted programming bit [Trimberger97b]. P0 P3 are the stored programming bits, while C0 C3 are the chip wide control lines which select the context to program or activate. Fast switching between contexts makes the grouping of the configurations into contexts slightly less critical, because if a configuration is on a different ....

S. Trimberger, D. Carberry, A. Johnson, J. Wong, "A Time-Multiplexed FPGA", IEEE Symposiumon Field-Programmable Custom Computing Machines, 1997.

....an full column of configuration information to be reconfigured at once, as in the Xilinx Virtex FPGA [Xilinx99] In contrast, a multi context FPGA includes multiple memory bits for each programming bit location. These memory bits can be thought of as multiple planes of configuration information [DeHon96, Trimberger97]. Only one plane of configuration information can be active at a given moment, but the device can quickly switch between different planes, or contexts, of already programmed configurations. In this manner, the multi context device can be considered a multiplexed set of singlecontext devices, which ....

....will fit within that area for a given programming architecture. The serial design is based on a two phase shift chain of programming bits, while the partial is formed of column and row decoders, with five transistor SRAM cells. The multi context design is based on a previously published design [Trimberger97]. To measure performance, caching algorithms were designed to control when configurations should be swapped in and out of the array for each of the FPGA programming architectures, and lower bound algorithms were also developed [Li00] Together, these algorithms define a range of performance ....

S. Trimberger, D. Carberry, A. Johnson, J. Wong, "A Time-Multiplexed FPGA", IEEE Symposium on Field-Programmable Custom Computing Machines, 1997.

.... technology can be found in [11] A description of the architectural design, circuit design and layout issues of an SRAM based FPGA can be found in [12] and [13] One variation of an SRAM based FPGA that some researchers have looked into is a DPGA (Dynamically Programmable Gate Array) 14][15] also known as Multiple Context FPGA. This architecture can have more than one configuration cell multiplexed for each programmable element. The cells are arranged in a manner that they provide other new sets of Evaluation of the OneChip Reconfigurable Processor 11 Reconfigurable processor ....

Trimberger, S., D. Carberry, A. Johnson and J. Wong. "A Time-Multiplexed FPGA", Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'97), April 1997, pp. 34-40.

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Steve Trimberger, Dean Carberry, Anders Johnson, and Jennifer Wong. A time-multiplexed FPGA. In J. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 22--28, Napa, CA, 1997.

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S. Trimberger, D. Carberry, A. Johnson, and J. Wong, "A Time-Multiplexed FPGA," Proceedings of the IEEE Workshop on FPGA Custom Computing Machines, pp. 22-28, 1997.

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S. Trimberger, D. Carberry, A. Johnson, and J. Wong, "A timemultiplexed FPGA," in Proc. IEEE Workshop FPGA's Custom Comput. Machines, J. Arnold and K. L. Pocek, Eds., Napa, CA, Apr. 1997, pp. 22--28.

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S. Trimberger, D. Carberry, A. Johnson, and J. Wong, "A timemultiplexed FPGA," in Proc. IEEE Workshop FPGA's Custom Comput. Machines, J. Arnold and K. L. Pocek, Eds., Napa, CA, Apr. 1997, pp. 22--28.

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Steve Trimberger, Dean Carberry, Anders Johnson, and Jennifer Wong, "A TimeMultiplexed FPGA," in Proceedings of IEEE symposium on FPGAs for custom computing machines, April 1997.

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Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A Time-Multiplexed FPGA. In: IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, (1997) 22--28.

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S. Trimberger, D. Carberry, A. Johnson, and J. Wong, "A time-multiplexed FPGA," in Proc. IEEE Symp. FPGAs Custom Computing Machines (FCCM), Napa Valley, CA, Apr. 1997, pp. 22--28.

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S. Trimberger, D. Carberry, A. Johnson, and J. Wong, "A timemultiplexed FPGA," in Proc. 5th IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM), 1997, pp. 22--28.

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S. Trimberger, D. Carberry, A. Johnson, and J. Wong, "A Time-Multiplexed FPGA," in Proceedings of IEEE symposium on FPGAs for custom computing machines, April 1997.

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Steve Trimberger, Dean Carberry, Anders Johnson and Jennifer Wong, "A Time-Multiplexed FPGA," Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 2228, April 1997.

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Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A time-multiplexed FPGA. In: Proc. 5th IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM). (1997) 22--28

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S. Trimberger, \A Time-Multiplexed FPGA", in Proc. of IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 22-28, 1997.

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Trimberger, S. A Time-Multiplexed FPGA. Proceedings FPGAs for Custom Computing Machines, FCCM 97, IEEE Cmputer Society, 1997.

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S. Trimberger, D. Carberry, A. Johnson, and J. Wong. A Time-Multiplexed FPGA. In the Proceedings of the FieldProgrammable Custom Computing Machines, pages 22--28, 1997.

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