I. R. Bahar and S. Manne, "Power and Energy Reduction Via Pipeline Balancing," in In Proceedings of ISCA, 1998. Home/Search Document Not in Database Summary Related Articles Check |
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Joint Local and Global Hardware Adaptations for Energy - Ruchira Sasanka Christopher (2002) (7 citations) (Correct)
....c 2002 ACM ISBN 1 58113 574 2 02 0010. 5. 00 ware adaptation, including dynamic voltage and frequency scaling, or DVS (e.g. 13, 14, 25, 27] and architecture adaptation (e.g. changing the instruction window size [6, 9, 11, 26] changing the number of functional units and or issue width [3, 23], and others [2, 4, 12, 15, 16, 22] This work concerns control algorithms for such hardware adaptations for multimedia applications, and is part of the Illinois GRACE project which seeks to coordinate system wide hardware and software adaptations [1] Two key questions must be addressed when ....
....applications, both without and with DVS. The basic approach adapting individual components to save energy without signi cant reduction in performance is similar to that previously proposed for work on non real time applications. Therefore, much of that work is applicable here as well [2, 3, 4, 6, 9, 11, 22, 23, 26]. The focus of our work is on the e ectiveness of local adaptation control algorithms for multimedia applications and their interaction with global architecture adaptation and DVS. We focus on two architecture adaptations varying instruction window size and varying the number of active ....
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R. I. Bahar and S. Manne. Power and Energy Reduction Via Pipeline Balancing. In Proc. of the 28th Annual Intl. Symp. on Comp. Architecture, 2001.
Routine based OS-aware Microprocessor Resource Adaptation for.. - Li, John (2003) (Correct)
....is projected to increase due to the increasing demands for system management activities, such as thermal sensor reading, energy accounting and power control for memory and I O devices [2] Clearly, in a power constrained environment, OS power saving needs to be addressed. However, previous studies [3, 4, 5] entirely focus on lowing power for useronly applications. To our knowledge, power saving and optimization for the OS itself have received little attention. 91 89 0 10 20 30 40 50 pmake gcc vortex sendmail fileman db jess javac jack postgres.select postgres.update osboot ....
....processor resources (with lower computational capabilities) matching the OS requirement. 0 0.5 1 1.5 2 2.5 IPC pmake vortex fileman jess jack p.update AVG gcc sendmail db javac p.select osboot User OS Figure 3. IPC of User and OS on an 8 issue Machine Current adaptation techniques [3, 4, 5, 11] rely on periodic sampling schemes to match program computational requirement with processor resources. However, we show in this paper that resource adaptation based on sampling window becomes less efficient when applied to the exception driven and short lived OS execution. Moreover, for large and ....
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R. I. Bahar et al., Power and Energy Reduction via Pipeline Balancing, In Proc. of ISCA, 2001.
Branch Prediction On Demand: an Energy-Efficient Solution - Chaver, Pinuel, Prieto, .. (2003) (Correct)
....dynamically adjust hardware resources to reduce energy consumption while still meeting application demand. Among other proposals, Albonesi et al. adjust the cache configuration [1, 3] Folegnani and Gonzalez disable empty instruction window entries [6] Bahar and Manne shut down functional units [2]. The concept of these approaches is similar, but the issue of on demand branch prediction is a bit more tricky. While any adaptation that results in performance degradation runs the risk of increasing energy consumption (due to fixed energy overhead per cycle) adaptation of branch predictor adds ....
R. Bahar and S. Manne. Power and Energy Reduction Via Pipeline Balancing. In International Symposium on Computer Architecture, pages 218--229, Goteberg, Sweden, June--July 2001.
Power-Aware Control Speculation through Selective Throttling - Aragón, González, González (2003) (1 citation) (Correct)
....[27] In [1] it is proposed to balance the clock rate dynamically to match the requirements of the instruction stream. In [7] it is minimized power consumption of functional units, exploiting the fact that the sizes of operands are often less than the size of the available functional units. In [5], Pipeline Balancing dynamically tunes the resources of a general purpose processor to the needs of the application by monitoring performance. In [11] energy consumption of the issue logic is reduced by dynamically re sizing the instruction queue and disabling the wake up of ready operands. In ....
R.I. Bahar and S. Manne. "Power and Energy Reduction Via Pipeline Balancing". Proc. of the Int. Symp. on Computer Architecture, 2001.
Power-Aware Control Speculation through Selective Throttling - Juan Arag Josogonzz (2003) (1 citation) (Correct)
....[27] In [1] it is proposed to balance the clock rate dynamically to match the requirements of the instruction stream. In [7] it is minimized power consumption of functional units, exploiting the fact that the sizes of operands are often less than the size of the available functional units. In [5], Pipeline Balancing dynamically tunes the resources of a general purpose processor to the needs of the application by monitoring performance. In [11] energy consumption of the issue logic is reduced by dynamically re sizing the instruction queue and disabling the wake up of ready operands. In ....
R.I. Bahar and S. Manne. Power and Energy Reduction Via Pipeline Balancing. Proc. of the lnt. Symp. on Computer Architecture, 2001.
Tuning Adaptive Microarchitectures - Dhodapkar, Smith (Correct)
....Multi configuration units With power becoming a critical consideration for general purpose microprocessors, several microarchitectural techniques have been proposed for reducing power consumption. There have been proposals for configurable caches and TLBs [2 4] issue windows [5, 6] and pipelines [7]. Almost all of these techniques focus on adapting the shape and size of the hardware to match the program requirements. For example, caches can be configured such that they are big enough to just fit the program s working set. If the working set is small, a large part of the cache can be shut ....
R. Bahar and S. Manne, "Power and Energy Reduction via Pipeline Balancing," Proc. of the 28 Intl. Sym. on Computer Architecture, July 2001.
Combining Software and Hardware Monitoring for Improved.. - Chi, Salem, Bahar, Weiss Self-citation (Bahar) (Correct)
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R. I. Bahar and S. Manne. Power and energy reduction via pipeline balancing. In Proceedings of the International Symposium on Computer Architecture, July 2001.
A Communication-Centric Approach To Instruction Steering - For Future Clustered (Correct)
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I. R. Bahar and S. Manne, "Power and Energy Reduction Via Pipeline Balancing," in In Proceedings of ISCA, 1998.
Performance Directed Energy Management for Main.. - Li, Li, David, Zhou, .. (2004) (Correct)
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R. I. Bahar and S. Manne. Power and energy reduction via pipeline balancing. In Proceedings of the 28th Annual Symposium on Computer Architecture, 2001.
Performance Directed Energy Management for Main.. - Li, Li, David, Zhou, .. (2004) (Correct)
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R. I. Bahar and S. Manne. Power and energy reduction via pipeline balancing. In Proceedings of the 28th Annual Symposium on Computer Architecture, 2001.
The Thrifty Barrier: Energy-Aware Synchronization in - Shared-Memory.. (Correct)
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R. Bahar and S. Manne. Power and energy reduction via pipeline balancing. In International Symposium on Computer Architecture, pages 218--229, Gothenburg, Sweden, June--July 2001.
Adaptive Pipeline Depth Control for Processor Power-Management - Aristides Efthymiou Jim (2002) (Correct)
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R. Bahar, S. Manne. Power and energy reduction via pipeline balancing. In Proc. ISCA'01, pages 218--229. June 2001.
A Large, Fast Instruction Window for Tolerating Cache Misses - Alvin Lebeck Jinson (Correct)
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R. I. Bahar and S. Manne. Power and Energy Reduction via Pipeline Balancing. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 218--229, July 2001.
Integrating Complete-System and User-level Performance/Power.. - Chen, al. (2003) (Correct)
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R. Bahar and S. Manne, "Power and Energy Reduction Via Pipeline Balancing", in Proc. 28th Ann. Int. Symp. Computer Architecture, 2001, pp. 218-229.
Cool-Fetch: A Compiler-Enabled IPC Estimation Based.. - Unsal, Koren.. (Correct)
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Bahar R. I., Manne S., "Power and Energy Reduction Via Pipeline Balancing, " Proceedings of the 28th International Symposium on Computer Architecture, ISCA28, June 2001.
Instruction History Management for High-Performance Microprocessors - Bhargava (2003) (Correct)
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R. I. Bahar and S. Manne. Power and energy reduction via pipeline balancing. In 28th International Symposium on Computer architecture, pages 218--229, May 2001.
Asynchronous Techniques for Power-Adaptive Processing - Efthymiou (2002) (Correct)
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R. Bahar and S. Manne. Power and Energy Reduction via Pipeline Balancing. In Proceedings of the International Symposium on Computer Architecture, pages 218--229. ACM Press, June 2001.
The Thrifty Barrier: Energy-Aware Synchronization in - Shared-Memory.. (Correct)
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R. Bahar and S. Manne. Power and energy reduction via pipeline balancing. In International Symposium on Computer Architecture, pages 218--229, Gothenburg, Sweden, June--July 2001.
Combining Intra-Frame With Inter-Frame Hardware Adaptations To.. - Sasanka (2002) (Correct)
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R. I. Bahar and S. Manne. Power and Energy Reduction Via Pipeline Balancing. In Proc. of the 28th Annual Intl. Symp. on Comp. Architecture, 2001.
Configurable Platforms with Dynamic Platform Management: An .. - Sekar, Lahiri, Dey (Correct)
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R. I. Bahar and S. Manne, "Power and energy reduction via pipeline balancing," in Proc. Int. Symp. Computer Architecture, pp. 218--229, July 2001.
An Adiabatic Framework for a Low Energy μ-Architecture &.. - Ramarao, Tyagi (Correct)
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R. Bahar and S. Manne. Power and energy reduction via pipeline balancing. Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001.
Speculative Software Management of Datapath-width.. - Pokam, Rochecouste, .. (2004) (Correct)
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Bahar, R.I., and Manne, S. Power and Energy Reduction Via Pipeline Balancing. In Proceedings of the 28th International Symposium on Computer Architecture, June 2001.
A Large, Fast Instruction Window for Tolerating Cache.. - Li, Koppanalil.. (2002) (Correct)
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R. I. Bahar and S. Manne. Power and Energy Reduction via Pipeline Balancing. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 218--229, July 2001.
Managing Multi-Configuration Hardware via Dynamic Working .. - Ashutosh Dhodapkar And (2002) (19 citations) (Correct)
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R. Bahar and S. Manne, "Power and Energy Reduction via Pipeline Balancing," Proc. of the 28 Computer Architecture, July 2001.
A Large, Fast Instruction Window for Tolerating Cache.. - Lebeck, Koppanalil.. (Correct)
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R. I. Bahar and S. Manne. Power and Energy Reduction via Pipeline Balancing. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 218--229, July 2001.
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