M. Griffin, G. Tahara, K. Knorpp, and W. Riley, "An 11-million Transistor Neural Network Execution Engine," Proc. of the 1991 IEEE Int. Conf. on Solid-State Circuits, 1991, pp. 180-181. Home/Search Document Not in Database Summary Related Articles Check |
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A Real-Time Clustering Microchip Neural Engine - Serrano-Gotarredona.. (1995) (Correct)
....level operation is demonstrated through the experimental testing of faulty chips. I. Introduction Two types of neural hardware engineers can be distinguished. The first designs general purpose hardware accelerators or systems that speed up neural algorithms running on conventional computers [4] [12] This kind of hardware allows considerable flexibility in the topology and operations of the neural systems. In this way algorithm researchers have a powerful tool to further develop neural algorithms and industry engineers have some attractive chips that significantly speed up their neural ....
M. Griffin, G. Tahara, K. Knorpp, and W. Riley, "An 11-million Transistor Neural Network Execution Engine," Proc. of the 1991 IEEE Int. Conf. on Solid-State Circuits, 1991, pp. 180-181.
Behavioral-Level Synthesis of Heterogeneous BISR.. - Guerra, Potkonjak.. (1993) (1 citation) (Correct)
.... of bit sliced devices for which BISR has been well addressed [Gre84, Kor85, Wey87, Has90] It has also been successfully applied for arithmetic logic unit byte slices [Sie92, Lev68] Other areas in which BISR techniques are being used include secondary storage systems [Pat88] massive parallelism [Gri91], wafer scale integration [Sat92] and systolic array designs [Lei85, Neg89] Note that BISR methodology is not limited to memory and execution units; Lewis, for example, proposed the use of a backup fault tolerant clock [Lew79] While all previous BISR techniques have been based on replacing a ....
M. Griffin, et al., "An 11-Million Transistor Neural Network Execution Engine," ISSCC, pp. 180-181, San Francisco, CA, 1991. Behavioral-Level Synthesis of Heterogeneous BISR Reconfigurable ASICs 27
Digital Neurohardware: Principles and Perspectives - Schönauer, Jahnke, Roth, Klar (1998) (1 citation) (Correct)
....the broadcast bus structure is exploited also in another way in the CNAPS system: the N6400 die measures about one square inch with more than 13 million transistors integrated. The yield is kept at an acceptable level by introducing redundancies and reconfiguring faulty elements after fabrication [5]. Out of 80 PNs integrated 64 PNs are used after test and reconfiguration, resulting in a 90 yield. Figure 2: Presentation of a neural network: conventional (left) weight matrix (middle) mapped N parallel (right) Figure 3: S and SN Parallelism 1 w 00 w 03 w 02 w 01 w 10 w 13 w 12 w 11 w ....
Griffin, M., Tahara, G., Knorpp, K. et al., 1991, An 11 million transistor neural network execution engine. IEEE Internation Conference on Solid-State Circuits, pages 180-181, 1991.
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