| J.J.T. Sousa, F.M. Gonalves, J.P.Teixeira, C. Marzocca, F. Corsi, T.W. Williams, "Defect Level Evaluation in an IC Design Environment", IEEE Trans. on CAD, vol. 15, n. 10, pp. 1286-1293, 1996. |
....phenomenon, which produces significantly more accurate yield estimates than theories that assume defects that are probabilistically independent. Despite the relevance of the clustering effect, many defect level models do not account for it [Williams and Brown, 1981, Agrawal et al. 1982, Sousa et al. 1996], but there are a few models that do [Seth and Agrawal, 1984, Singh and Krishna, 1996] In [Seth and Agrawal, 1984] the clustering effect is implicitly taken into account by using the negative binomial distribution for the number of defects in a chip. In [Singh and Krishna, 1996] defect clustering ....
....Equation (1.6) lim ff 1 (1 ff ) Gammaff = e Gamma : 1.7) Substituting Equation (1.6) in Equation (1.1) we obtain an expression for the Williams Brown model which is preferred in this work: DL = 1 Gamma e Gamma(1 Gamma Omega Gamma (1. 8) Defect Level and Clustering Effect 5 In [Sousa et al. 1996] it is suggested that the reason why the Williams Brown formula combined with the stuck at fault coverage T cannot track experimental fallout data is the fact that, unlike T , in the real fault coverage Omega each fault should be weighted with its probability of occurrence. In [Sousa et al. ....
[Article contains additional citation context not shown here]
Sousa, J. J. T., Goncalves, F. M., Teixeira, J. P., Marzocca, C., Corsi, F., and Williams, T. W. (1996). "Defect Level Evaluation in an IC Design Environment". IEEE Trans. on CAD, 15:1286--1293.
....model is easily evaluated, but a reliable technique is needed to evaluate the accuracy of the fault model. The problem of measuring the accuracy of a functional fault model for verification is analogous to the problem of relating stuck at fault coverage to defect coverage for manufacture test [2]. In both problems, an abstract high level fault model must be evaluated by comparison to a low level defect model. The defect model is tied directly to the source of the defects, while the fault model is an abstraction of the behavior caused by defects. In the case of manufacture test, the defect ....
J. T. deSousa, F. M. Goncalves, J. P. Teixeira, C. Marzocca, F. Corsi, and T. W. Williams. Defect Level Evaluation in an IC Design Environment. IEEE Transactions on Computer-Aided Design, 15(10):1286--1293, October 1996.
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J.J.T. Sousa, F.M. Gonalves, J.P.Teixeira, C. Marzocca, F. Corsi, T.W. Williams, "Defect Level Evaluation in an IC Design Environment", IEEE Trans. on CAD, vol. 15, n. 10, pp. 1286-1293, 1996.
No context found.
#J.J.T. Sousa, F.M. Gonalves, J.P.Teixeira, C. Marzocca, F. Corsi, T.W. Williams, "Defect Level Evaluation in an IC Design Environment", IEEE Trans. on CAD, vol. 15, n. 10, pp. 1286- 1293, 1996.
....for yield loss. They also account for the defect clustering phenomenon, which produces signi cantly more accurate yield estimates than theories that assume defects that are probabilistically independent. Despite the relevance of the clustering e ect, many defect level models do not account for it [1, 2, 3], but there are a few models that do [4, 5] In [4] the clustering e ect is implicitly taken into account by using the negative binomial distribution for the number of defects in a chip. In [5] defect clustering is exploited to identify dice with di erent DL values in the same wafer. These dice ....
....one combination of values. This means that the parameters are related in a particular way; any combination of values that respects this relation will do. Also, albeit the clustering e ect is accounted for, the e ect of varying its intensity has not been studied. 2. 4 The de Sousa et al. model In [3], it is suggested that the Williams Brown formula is accurate if the fault coverage is obtained by weighting layout extracted faults according to probability of occurrence. This was proven to be equivalent to expressing in the following way: P m i=1 A i D i P n i=1 A i D i ; 11) where ....
[Article contains additional citation context not shown here]
J. J. T Sousa, F. M. Goncalves, J. P. Teixeira, C. Marzocca, F. Corsi, and T. W. Williams. \Defect Level Evaluation in an IC Design Environment ". IEEE Trans. on CAD, 15:1286-1293, October 1996.
....realistic weighted fault coverage measure. DL = 1 Gamma Y 1 Gamma Omega (3) Each fault is weighted by a factor w j = Gammaln(1 Gamma p j ) 4) that reflects its probability of occurrence p j and is calculated in terms of the physical defect densities and critical areas [2] It can be shown [17], that w j has the physical significance of the average number of inducing defects for fault j, i.e. w j = A j D j , where A j is the critical area of fault j and D j is its average defect density. As a consequence, Y and Omega are given respectively by: Y = e Gamma P n j=1 w j (5) ....
J.J.T Sousa, F.M. Goncalves, J.P. Teixeira, C. Marzocca, F. Corsi, and T.W. Williams. "Defect Level Evaluation in an IC Design Environment ". IEEE Trans. on CAD, 15:1286--1293, October 1996.
No context found.
J.J.T. Sousa, F.M. Gonalves, J.P.Teixeira, C. Marzocca, F. Corsi, T.W. Williams, "Defect Level Evaluation in an IC Design Environment", IEEE Trans. on CAD, vol. 15, n. 10, pp. 1286-1293, 1996.
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