M. Horowitz, C. Ken, and S. Sidiropoulos. High speed electrical signalling: Overview and limitations. IEEE Micro, 18:12--24, 1998. Home/Search Document Details and Download
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....scaled supply voltage environment offers automatic slew rate control without the need for additional hardware. 4.3. 1 High Impedance Drivers High speed links commonly rely on high impedance drivers to efficiently convert binary data bits into electrical signals that propagate through the channel [19]. These signals are generated via a current source that turns on and off depending on the polarity of the transmitted data. Figure 4.15 presents a schematic of a driver that utilizes a current source that actively pulls up the output to generate signals in the channel that swing relative to ....
....which is why interfaces slew rate limit their outputs where edges ctrl[n:0] m[n] m[0] n 1 Figure 4.18. transmitter output swing control consume a quarter to a third of the bit time. In conventional designs, limiting the slew rate can be difficult, and several approaches have been published [19], 26] 9] However, a dynamically regulated supply voltage environment again provides the process and environment monitoring required to automatically control the output slew rate without any additional hardware. The core DLL locks the delay of inverters in the delay line to half a clock period. ....
M. Horowitz, et. al., "High-speed electrical signalling: Overview and limitations," IEEE Micro, vol. 18, no. 1, Jan.-Feb. 1998, pp.12-24.
High Performance Inter-Chip Signalling - Sidiropoulos (1998) (2 citations) (Correct)
....noise sensitivity, while main 119 taining the low power dissipation of static CMOS buffers. Based on a simple technology independent performance metric, it can be argued that the performance of the circuits presented in this thesis will continue to scale with improving fabrication technology [72]. This has been demonstrated by porting both the integrating receiver and clocking circuits of Chapters 4 and 5 to a 0.25 m CMOS technology. The scaled version of the circuits achieve a transfer rate of 2 Gbps pin even when operating in a pseudo differential signalling mode [71] At these transfer ....
M. Horowitz, K. Yang, S. Sidiropoulos, "High-speed electrical signalling: Overview and limitations," IEEE Micro, vol.18, no.1, pp. 12-24, Jan.-Feb. 1998.
Precision CMOS Receivers for VLSI Testing Applications - Weinlader (2001) Self-citation (Horowitz) (Correct)
....specified timing. Building high speed pin electronics with precise timing that can scale with the performance of CMOS parts is a significant challenge. The I O frequencies of CMOS parts have historically scaled in a very limited manner primarily due to signal integrity issues at the system level [15]. This has been beneficial for test because the same tester could be used to test multiple generations of CMOS parts. But eventually higher speed I O is required because insufficient chip I O bandwidth limits the part functionality. This problem has been partly addressed by increasing the ....
M. Horowitz, et. al., "High-speed electrical signalling: Overview and limitations," IEEE Micro, vol. 18, no. 1, Jan.-Feb. 1998, pp.12-24. 96
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....to the slow and fast process corners for the PMOS transistors. Jitter in the clock that strobes the synchronization flip flops to the current cells can significantly degrade the performance of the D A converter. Since the jitter increases linearly with the number of buffering stages used [17], it is important to minimize the number of buffers used to Falakshahi, Yang, and Wooley: A 14 bit, 5MHz Digital to Analog Converter Using Multi bit Sigma Delta Modulation 12 generate the clock that drives the sensitive synchronization flip flops. This clock is generated separately from the clock ....
Mark Horowitz, Chih-Kong Ken Yang and Stefanos Sidiropoulos,"High Speed Electrical Signalling: Overview and Limitations," IEEE Micro, pp 12-24, Jan./Feb. 1998.
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M. Horowitz, C. Ken, and S. Sidiropoulos. High speed electrical signalling: Overview and limitations. IEEE Micro, 18:12--24, 1998.
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