J. C. Mogul and A. Gorg, "The Effect of Context Switches on Cache Performance, " Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 75--84, April 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....invalidations introduce an additional miss rate component. In this paper, we focus on the multiprogramming component of the miss rate. Understanding this component is important because significant evidence exists showing that it is the chief determinant of the miss rate in large caches [6, 7]. While the model for the multiprogramming component of misses developed in [4] can be used to yield fast estimates of cache performance, it is not simple, and hence does not offer much S Number of cache sets (or rows) u Working set size (in blocks) of each process p Number of processes or the ....

....predicted cache miss rates with those obtained from trace driven simulation for various cache sizes and with different degrees of multiprogramming. Trace driven simulation [15] is a popular technique for cache evaluation, especially since address traces for various workloads are publicly available [16, 7]. This section first describes our simulation methodology and then analyzes the results. 6.1 Simulation Methodology Our experiments with the model will use both real traces of multiprogrammed workloads and replicated traces. Replicated traces are like multiprogrammed traces, but they are ....

Jeffrey C. Mogul and Anita Borg. The Effect of Context Switches on Cache Performance. In ASPLOS-IV Proceedings, pages 75--84, April 1991.

....threshold between hardware based and software based protection depends on the amount of work done in the service, but the evolution of technology will favor hardware based protection schemes. The first two assertions are not surprising. The third is different from what earlier work [Chen 93] Mogul 91] Bersh 92] implies, and is probably a result of changes in hardware architectures. The fourth is counter intuitive since it seems to say that sharing is better than copying for small data objects, but not for larger ones. The final one is most significant and, perhaps, most controversial. 3 2. ....

....although cpu performance has improved significantly over the last few years, operating system performance, especially context switch times have clearly not kept pace. His work did not analyze the reasons for this behavior. The impact of context switches on the cache performance is analyzed in [Mogul 91] This work demonstrated that the cost of cache refills can dominate overall cost of a context switch. Chen and Bershad [Chen 93] analyzed the effect of the system software decomposition on the memory subsystem performance. The work argues that the separation of operating system functionality ....

J.Mogul, A. Borg, The Effect of Context Switches on Cache Performance, 4th Int'l Conf Architectural Support for Programming Languages and Operating Systems, ACM, pp. 75-85, 1991

....to set up correct and representative scenarios to be measured. If for instance the worst case execution time (WCET) is to be measured, one must set up an execution path that leads to the WCET. Execution time and other performance issues can either be statically analyzed [1, 2, 3, 4] or simulated[5, 6], or measured directly on the target system[4, 7] The advantage of static methods is that they are safe if the system model and analysis method are correct and compatible with each other. The hard part is to add complex structures into the model like pipelining, cache memories, DMA and other ....

....was measured to 86,9 s , which means that the total preemption delay is 282.4s . In relative terms the major part of the context switch cost, or 195.5 282.4 = 69 , is cacherelated. It is quite interesting that the CRPD is almost the same compared to Mogul and Borg s measurements a decade ago[5], which were 10 400 s . During this time the processors have become magnitudes times faster and this means that the CRPD has grown in relative terms. The method to get the CRPD is practicable to get a safe value that is directly useable in a scheduling algorithm. Even if the value is ....

Jeffrey C. Mogul and Anita Borg. The effect of context switches on cache performance. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 75--84, Santa Clara, CA, USA, April 1991.

....however, focuses on whether the modeling of multiprogramming affects predictor behavior. Since we find that it typically does not, it is unnecessary (and prohibitively expensive) to obtain IPC measurements. Some similar work has explored caching in the face of context switching. Mogul and Borg [16] examined how cache hit rate varies after a context switch and noted that the cost of context switches, in terms of how it affects cache performance, can guide cache design. Hwu and Conte [10] studied the worst case susceptibility of programs to context switching. In their study, they develop ....

J. C. Mogul and A. Borg. The effect of context switches on cache performance. Tech. Note TN-16, DEC WRL, Dec. 1990. 20

....Tunix interleaves the traces generated by multiple tasks into a global trace buffer that is periodically emptied by a trace processing program. These researchers also experimented with instrumenting the Tunix kernel itself, although they do not report any results obtained from these traces [Mogul91]. Chen continued this work by porting a version of epoxie to a MIPS based DECstation running Ultrix and Mach 3.0 to produce traces from single task workloads including the user level X and BSD servers, and the kernel itself [Chen93a; Chen93c] As a rule, static code instrumentation cannot handle ....

Mogul, J. C. and Borg, A. The effect of context switches on cache performance. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, ACM, 75-84, 1991.

....among concurrent processes. of cache sizes that are large enough to have a considerable number of conflicts but not large enough to hold all the working sets. However, these models work only for long enough time quanta, and require information that is hard to collect on line. Mogul and Borg [12] studied the effect of context switches through trace driven simulations. Using a timesharing system simulator, their research shows that system calls, page faults, and a scheduler are the main sources of context switches. They also evaluated the effect of context switches on cycles per ....

J. C. Mogul and A. Borg. The effect of context switches on cache performance. In the fourth international conference on Architectural support for programming languages and operating systems, 1991.

....how overall system performance is affected. Our work, however, focuses on whether the modeling of multiprogramming affects predictor behavior. Since we find that it typically does not, it is unnecessary (and prohibitively expensive) to obtain IPC measurements. Similar work by Mogul and Borg [16] has explored caching in the face of context switching. They examined how cache hit rate varies after a context switch and noted that the cost of context switches, in terms of how it affects cache performance, can guide cache design. Hwu and Conte [10] studied the worst case susceptibility of ....

J. C. Mogul and A. Borg. The effect of context switches on cache performance. Tech. Note TN-16, DEC WRL, Dec. 1990.

....accurate results, but simulation time is often long. Hardware monitoring can dramatically speed up the process [26] however, it is limited to the particular cache configuration. As a result, both simulations and hardware monitoring can only be used to evaluate the effect of context switches [14, 10]. Moreover, simulations and monitoring rarely provide intuitive understanding making it difficult to improve cache performance. To provide both performance prediction and insight into improving performance, analytical cache models are required. We use our model to determine the best cache ....

....are noticeable for a mid range of cache sizes that are large enough to have a considerable number of conflicts but not large enough to hold all the working sets. However, these models work only for long enough time quanta, and require information that is hard to collect on line. Mogul and Borg [14] studied the effect of context switches through trace driven simulations. Using a timesharing system simulator, their research shows that system calls, page faults, and a scheduler are the main sources of context switches. They also evaluated the effect of context switches on cycles per ....

J. C. Mogul and A. Borg. The effect of context switches on cache performance. In the fourth international conference on Architectural support for programming languages and operating systems, 1991.

.... this problem is to add code specially designed to execute the loop a constant few iterations (Hwu calls this type of structure a superblock in [75] There is also a secondary cost of loop unrolling in some architectures caused by the additional cache misses due to the increased code size [115][116][40] 171] The efficiency of loop unrolling quickly drops in relation to the size of original loop inefficiency and the unroll count. It is easy to see why this is the case. Each additional time the loop is unrolled, the idle portion of one iteration is removed. The idleness reduces at the rate ....

.... . MMMMMMMMMM 0 10 50 100 110 120 130 140 150 200 0 10000000 20000000 30000000 40000000 50000000 Unroll Size maximum insns B 128w J 256w H 512w F 1k 2k . 4k 8k 16k M 32k 64k 156 4. 4 Context Switch Effects In [116] Mogul and Borg find a performance degradation due to context switching of 1 to 7 depending on the program mix and cache design. This study, and another by Steenkiste [171] show that the additional effect of having a larger code size when context switching might be 10 of cost of context ....

J. C. Mogul, A. Borg, The Effect of Context Switches on Cache Performance, Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 1991, vol. 19, pp. 75-84.

....CPU resources. Industrial developers are today in a great need of real values to implement new software based products on highperformance processors. To the best of our knowledge the only work that has been presented to measure the CRPD is Mogul and Borg s trace driven simulation of a UNIX system [9]. Mogul and Borg measured the delay (#)to### # ##### of a task. The traces were however not taken from a real time system and all the time slices were of equal size. The cache memories are today larger and more complex than those the simulations were performed at. Performance estimation on cache ....

Jeffrey C. Mogul and Anita Borg. The effect of context switches on cache performance. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 75--84, Santa Clara, CA, USA, April 1991.

....Thus past studies have shown significant dependence of overall performance on cache misses and we observe that cache misses could be 15 to 35 higher if operating system activity was considered. Others have studied the effect of context switches on cache performance in non x86 environments [16, 17]. Rosenblum et al.# studied the execution of some applications under the effects of a full system simulation [8] SimOS has intensified research using full system traces, however, it has not been particularly helpful for the x86 domain. Evers et al.# analyzed the effect that context switches have ....

J. C. Mogul and A. Borg, "The effect of context switches on cache performance, " Tech. Rep. TN-16, Digital Western Research Lab, Palo Alto, CA, USA, Dec 1990.

....0.040 Table 10.3: Reduction in application throughput due to clock interrupts as a function of frequency and cache state of re establishing the working set can be almost 3 ms an enormous penalty when compared to the in kernel context switch cost on the order of 10 s. In 1991 Mogul and Borg [62] showed that the cache performance cost of a context switch could dominate overall context switch performance. Furthermore, they speculated that in the future the increasing cost of memory accesses in terms of CPU cycle times would make the impact of the cache performance part of context switch ....

Jeff Mogul and Anita Borg. The Effect of Context Switches on Cache Performance. In Proc. of the 4th International Conf. on Architectural Support for Programming Languages and Operating Systems, pages 75--84, Santa Clara, CA, April 1991. Bibliography 167

....He studies the effects on the cache of the interaction between the kernel process and user processes in a VAX system. His results show that about 51 of the overall cache misses of user processes are caused by interference induced by the kernel process. Similar research was done by Mogul and Borg [12]. They quantify the additional cache misses caused by context switching in a UNIX environment. Their results show up to 8 difference in Clocks Per Instruction (CPI) between the system with a private cache for each process and the system where a single cache is shared by all the processes. ....

J. C. Mogul and A. Borg. The effect of context switches on cache performance. In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 75--84, 1991.

....cache misses. This is because preemption due to unrelated, even lower priority, activities can occur frequently and at arbitrary instants. Not only does this result in loss of CPU capacity to unnecessary context switches, it also increases the likelihood of disturbing the footprint in the cache [30], unless the cache is suitably partitioned [31] This is particularly true for preemption caused by external events such as network interrupts. One can account for the cache miss penalty due to preemption via careful schedulability analysis [32] but frequent preemption still degrades available ....

J. Mogul and A. Borg, "The effect of context switches on cache performance," in Proc. Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 75--85, April 1991. 29

....element (PE) it is executing upon. Depending on the underlying OS and hardware platform, performing a context switch may involve dozens to hundreds of instructions due to the flushing of register windows, instruction and data caches, instruction pipelines, and translation look aside buffers [26]. Synchronization mechanisms are necessary to serialize access to shared objects (such as messages, message queues, protocol context records, and demultiplexing tables) related to protocol processing. Certain methods of parallelizing protocol stacks incur significant synchronization overhead from ....

J. C. Mogul and A. Borg, "The Effects of Context Switches on Cache Performance," in Proceedings of the 4 th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), (Santa Clara, CA), ACM, Apr. 1991.

....fine grained parallel programs. These latencies are due to both communication and synchronization among parallel computations. Counteracting the benefits of multithreading is the cost of context switching, which includes both direct overhead and the indirect cost of impaired cache performance [MB91] Two different approaches to lowering the costs of frequent context switches are bringing the programming model closer to the architecture (as is done by Active Messages [vECGS92] and bringing the architecture closer to the programming model s needs (as is done by the MIT J Machine [DFK ....

Jeffrey C. Mogul and Anita Borg. The effect of context switches on cache performance. In Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, April 1991.

....which is organized as a 4 way set associative with line size of 32 words. The time slice for a trace to interleave is 50,000 clock cycles and the probability that the task will migrate at the end of its time slice is 5 . Since only a few of the previous papers regarding cache coherent protocols [8] take into consideration the effect of process migration, we start our comparison by looking at how the performance of the system changes as a function of the number of processors in a system where no migration is assumed. Later on we will present the effect of the task migration on these ....

J. C. Mogul and a. Borg. "The Effect of Context Switches on Cache Performance". In the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 75-84, April 1991.

....usage appropriately for each application. In [Ander91] the technique is called scheduler activation s and in [Tucker93] it is called process control . The significant negative performance impact of thread imbalance on these commodity processor based parallel processing systems was identified in [Ander91,Tucker93,MoBo90]. In [Tucker93] the negative performance impact was broken down into its component causes and carefully measured using the SPLASH [SPLASH] benchmark applications. These issues are explored further in Chapter 2. Recent work in [YueLilja95,YueLilja95a,LiuLilja96] is most closely related to the ....

....overall efficiency is improved if the program with poor speedup operates with fewer threads. 39 As the speed of the CPU s has increased and the increasing reliance on data resident in cache, the problem of a context switch corrupting cache has become an increasing performance impact. In [MoBo90], when a compute bound process was context switched on a cache based system, the performance of the application was significantly impacted for the next 100,000 cycles after the process regained the CPU. The context switch still had a small negative impact on performance up to 400,000 cycles after ....

J. C. Mogul and A. Borg, The Effect of Context Switches on Cache Performance, DEC Western Research Laboratory TN-16, Dec., 1990. http://www.research.digital.com/wrl/techreports/ /abstracts/TN-16.html

No context found.

J. C. Mogul and A. Gorg, "The Effect of Context Switches on Cache Performance, " Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 75--84, April 1991.

No context found.

J. C. Mogul and A. Borg, "The Effects of Context Switches on Cache Performance," in Proceedings of the 4 th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), (Santa Clara, CA), ACM, Apr. 1991.

No context found.

Jeffrey C. Mogul and Anita Borg. The effect of context switches on cache performance. In Proceedings of Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (Santa Clara, CA), pages 75--84, 1991.

No context found.

J. C. Mogul and A. Borg. The effect of context switches on cache performance. In Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, pages 75--84. ACM Press, 1991. 14

No context found.

Jeffrey C. Mogul and Anita Borg. The effect of context switches on cache performance. In Proceedings of Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (Santa Clara, CA), pages 75--84, 1991.

No context found.

Jeffrey C. Mogul and Anita Borg. The effect of context switches on cache performance. In ASPLOS [ASPLOS1991], pages 75--84.

No context found.

J. C. Mogul and A. Borg. The Effect of Context Switches on Cache Performance. In the 4th Int'l Conference on Architectural Support for Programming Languages and Operating Systems, pp. 75-84, April 1991.

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