B. S. Davie, \A Host-network Interface Architecture for ATM," ACM Proc. Sigcomm, pp. 307-16, September 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....has forced the networking community to look into ways of overcoming the bottlenecks of current workstation architectures in order to provide that bandwidth to applications. Two interesting approaches were Hewlett Packard s Jetstream Afterburner project [Watson93] and Bellcore s Osiris ATM adapter [Davie91], Druschel94] The former opted to provide common data path operations (checksumming and low level demultiplexing) in hardware without any programmability; the latter project offered a completely programmable processing engine (CPU and memory) on the adapter card which could be programmed as ....

Bruce S. Davie; "A Host-Network Interface Architecture for ATM", Computer Communication Review, Volume 21, Number 4 (September 1991), pp.307--315.

....used by a group at HP Labs in Bristol in a series of network adapters including Medusa [18] Afterburner [28, 52] and Jetstream [38] Two more high performance network adapters were developed at about the same time. Traw and Smith [74, 75, 76] implemented an adapter for the IBM RS 6000 and Davie [29, 30, 31] implemented one for DEC workstations. The performance of TCP implementations have been extensively studied, most notably by Clark et al. 26] One important conclusion from their analysis was that message copying contributed to a large part of the processing time. Their work were followed by ....

Bruce S. Davie. A host-network interface architecture for ATM. In SIGCOMM '91 Conference Proceedings, pages 307--315, Zurich, Switzerland, September 3--6, 1991. ACM SIGCOMM Computer Communication Review, 21(4).

....reaches to the host. In that case, both TCP IP and ATM related protocols reside on the host. This closer coupling of transport leveland network levelprotocols facilitates their exchange of information regarding individual conversations. ATM is rapidly gaining popularity for local area network use[2,4,7,17,28], so that future wide area ATM networks will indeed reach to individual hosts. Amajor motivation behind ATM is its ability to support traffic from non traditional sources, such as audio and video, as well as traffic from the traditional TCP sources discussed in this paper.Nontraditional traffic ....

B. S. Davie, "A Host-Network Interface Architecture for ATM," Proc. of ACM SIGCOMM '91,Zurich, Switzerland, September,1991.

....and tuning of operational internet networks. Until now, research in the areas of trac engineering has primarily focused on measurement and control aspects of intra domain routing and resource allocation. Techniques already in use or in advanced development include Asynchronous Transfer Mode (ATM) [128, 129], Frame Relay overlay models [130] Multiple Protocol Label Switching (MPLS) 131] and constraint based routing (also known as QOS routing) 132] Many open problems remain to be solved to extend these solutions across autonomous system boundaries, and this has been an active research area. For ....

B. S. Davie, \A Host-network Interface Architecture for ATM," ACM Proc. Sigcomm, pp. 307-16, September 1991.

....by the University of Pennsylvania [17] 18] for the AURORA gigabit test bed. Their interface is designed for the IBM Microchannel bus and the RS 6000 workstation using DMA to transfer data between main memory and the interface board. The Bellcore ATM interface is another example of a similar design [5][6] Another approach is the zero copy host interface architecture [12] Its main idea is to transfer data directly with DMA between buffers in the user process address space and the interface hardware. This design has potentially higher performance capabilities, but has also a number of not yet ....

Bruce S. Davie. A host-network interface architecture for ATM. In SIGCOMM '91 Conference Proceedings, pages 307--315, Zrich, Switzerland, September 3-- 6, 1991. ACM SIGCOMM Computer Communication Review, 21(4).

....adapter can readily distinguish cells from different connections and treat them differently (i.e. early demultiplexing) Figure 1 shows the architecture of the generic ATM adapter that we will use as the basis for our discussion in the following sections. Several research and commercial adapters [10, 12, 8] follow this architecture. The adapter sits on the host I O bus and has the following components: Xmit: a transmit VC table with VCs (virtual connections) open for transmit. Associated with each open VC is per VC state and, if a packet is being transmitted, a pointer to one or more buffer ....

Bruce S. Davie. A Host-Network Interface Architecture for ATM. In Proceedings of the SIGCOMM '91 Symposium on Communications Architectures and Protocols, pages 307--315. ACM, September 1991.

.... Supporting ILP and ALF Extended abstract Bengt Ahlgren E mail: bengta sics.se Per Gunningberg E mail: per sics.se Swedish Institute of Computer Science Box 1263, S 164 28 Kista, Sweden October 25, 1994 Summary The memory bandwidth is one of the major performance bottlenecks [Dav91, LA93, DAPP93, DWB 93, ST93] limiting high speed communication for workstation class computers. In many of the current network interface architectures, the data is transferred to and from the memory several times, e.g. due to software copying between user and kernel address spaces. ILP ....

Bruce S. Davie. A host-network interface architecture for ATM. In SIGCOMM '91 Conference Proceedings, pages 307--315, Zurich, 5 Switzerland, September 3--6, 1991. ACM SIGCOMM Computer Communication Review, 21(4).

....performance puts more and more stress on the end host. As a result, there have recently been several efforts to experiment with different points in the design spectrum: 1) Nector s communications adaptor board (CAB) 1] 2) Network Adaptor Board (NAB) 2] and, 3) Aurora gigabit network testbed [3]. Each of these architectures implements one or more protocols on the network device in the case of CAB, it is an entire protocol suite; in the case of NAB, it is a single high level (transport) protocol; and in the case of Aurora, it is a single low level protocol. This paper introduces ....

B. S. Davie, A Host-Network Interface Architecture for {ATM}. Proceedings SIGCOMM 91ConferenceonCommunicationsArchitecturesandProtocols', 1991.

.... processors moves in cycles over time; they referred to this as the wheel of reincarnation [MS68] Over the last decade, numerous hardware experiments were conducted and suggestions were made for putting more functionality into the network adapter [Kan88, CSSZ90, Che87, Sid91, DWB 93, Dav91, TS91, BJM 96, SWR91, BPP91, DPD91, TP96] Most of the more radical features have not been accepted into mainstream adapters. Some of these approaches have not been adopted into the mainstream because they are specific to Open Systems Interconnection (OSI) or other protocols. Others have ....

Bruce S. Davie. A host-network interface architecture for ATM. In Proc. SIGCOMM '91

....Despite rapid advances in workstation processor and memory subsystem performance, the next generation of high speed (Gbps) wide area networks threatens to exceed the data management capabilities of the hosts. To assist these hosts, specialized host interfaces are being developed at Penn, Bellcore [4], Carnegie Mellon Fore Systems [3] and elsewhere. The host interface work at Penn has been centered on developing a high performance host interface for workstation hosts in the AURORA Gigabit Testbed environment [2] We have chosen to focus on workstations since we believe that they will be the ....

Bruce S. Davie, "A Host-Network Interface Architecture for ATM," in Proceedings, SIGCOMM 1991, Zurich, SWITZERLAND (September 4-6, 1991), pp. 307-315.

....interface takes a lot of time, the design of the HIF should not force the host to copy data between primary memory and the HIF. To avoid this the HIF is based on a shared memory that is mapped into the primary memory by the host. It can be accessed both by the host and the HIF (see for instance [4]) In the shared memory, the host writes data to be sent on the network, and reads data received from the network. The shared memory is divided into equally sized buffers (of typically 1 10 Kbyte) where each buffer can store one packet. Further, the host reads and writes control information in a ....

B. S Davie, "A Host-Network Interface Architecture for ATM," In Proc. ACM SIGCOMM `91, Zurich, Sep. 1991.

....receiving host, a buffer management scheme at the host interface is described which makes the connection setup without involving the host. 4.1. Implementation To support the fast access scheme, support for fast buffer management is realized on the host interface board. The host interface (HIF) [11], 19] sends and receives data and implements the SAR protocol (Chap 2.1. The interface is based on a shared memory to reduce copying of data between primary memory and the host interface [9] The number of transfers over the system bus, which is a bottleneck in the workstation [7] is then ....

B. Davie, "A Host-Network Interface Architecture for ATM", In Proc. ACM SIGCOMM `91, Sept. 1991, Zrich, Switzerland.

.... SUN, IBM, HP [25] DEC [74] National Semiconductors [86] and Fore Systems [22] The 622 Mbit s ATM interface for DEC Turbo Channel designed at Bellcore uses a flexible design with a combination of custom hardware and a pair of Intel 960 processors, one for transmitting and one for receiving [27] [28] At the University of Pennsylvania, an interface for an IBM RS 6000 is designed that consists entirely of dedicated hardware [12] 83] All cell processing is done in hardware on the interface board and the interface uses clocked interrupts for its state exchange protocol. In May 1993, ....

B. S. Davie, "A Host-Network Interface Architecture for ATM," In Proc. ACM SIGCOMM `91, Zurich, Sep. 1991. 65

....AIB HOST AIB HOST AIB HOST AIB HOST AIB HOST AIB . cluster1 cluster0 cluster n cluster2 . ATM Network . HOST AIB S S S S S S S S S: switch Figure 1: Overview of An ATM LAN. high speed data transfer between host and network. There have been several interfaces designed for ATM networks [8][9] 10] Comparing AIB with the existing designs, we can highlight the following three improved features. Firstly, we design a DM CA (Direct Memory Cache Access) controller to access host s cache when there is a cache hit, or host s memory with a cache miss. Secondly, the DM CA has an internal ....

Davie,B.S. "A Host-Network Interface Architecture for ATM," Proc. of SIGCOMM '91.

....CPU interfaces. Given different network and processor technologies, the relative importance of these components may change; by isolating the components, we can see how the performance of each scales with technology change. Controllers targeted for high throughput have been well studied in the past [5, 24, 38, 68]. However, latency is often the overriding concern in distributed systems, and consequently, for the most part, this chapter considers the impact of the controller on this aspect of communication performance. Given the increases in processor and network speed, it is natural to hypothesize that low ....

....example, on a 155 Mbit sec ATM network, individual cells, which are fixed size 53 byte packets, can arrive at the host once every 2.7 microseconds. In order to isolate the host from frequent interrupts and protocol processing overheads, some designs migrate functionality into the controller [24, 68]. However, the migration of too much functionality into the controller can impact the latency of processing network messages. In addition, if the controller presents a complex interface to the host, there could be additional software latency introduced by the host device driver in managing the ....

Bruce S. Davie. A host-network interface architecture for ATM. In Proceedings of the 1991 SIGCOMM Symposium on Communications Architectures and Protocols, pages 307--315, September 1991.

....interface design. The kernel interface copying may be eliminated by allowing the inter ATOMIC: A Low Cost, Very High Speed LAN 17 of 22 face to share access to the kernel network queues. Packets may then be stored directly into those queues on input and retrieved from the queues on output [11]. This requires that the interface be sufficiently flexible that it can manipulate kernel data structures. The Mosaic CPU in ATOMIC provides such flexibility. The modifications that would allow elimination of kernel interface data copying are straightforward in BSD UNIX. Elimination of the second ....

....Transfer Mode (ATM) has been suggested as an implementation technology for local as well as wide area networks [22] 6] ATM messages are of fixed length. Each is 53 bytes long with five bytes reserved for header, leaving a 48 byte payload. Several teams are creating prototype ATM host interfaces [11][12] 8] The Autonet follow on, AN2, will have ATM switches [27] ATOMIC sends variable length packets and it uses the distributed computational and routing capability of a mesh. This sets ATOMIC well apart from ATM based LANs. The fragmentation and reassembly required when ATM carries higher ....

Davie, B. S. "A Host-Network Interface Architecture for ATM", Proceedings of SIGCOMM -91, pp. 307-315, August 1991.

....networks. Research projects such as VMTP [23] and x kernel [24] represent examples of numerous efforts to construct frameworks for high performance transport protocol implementations. In order to further improve efficiency, new ATM host network interface designs have been proposed by Davie [25], Traw and Smith [26] and Moors and Cantoni [27] where the software bottleneck is reduced by providing hardware support for several aspects of protocol processing. Other researchers are investigating parallel computing on ATM networks. Although we have concentrated on collective communication in ....

B. S. Davie, "A host-network interface architecture for ATM," ACM Communication Review, pp. 307--315, 1991.

....advantage of aggressive workstation technology improvements. Penn s Micro Channel Architecture host interface is not the only one being designed for the AURORA Testbed environment. Davie of Bellcore [11] reports on a host interface design for the TurboChannel bus of the DECStation 5000 workstation [12]. The design relies on an Intel 80960 RISC microcontroller to perform the protocol processing and flow control for a trunk group of four STS 3c lines (622 Mbps) Powerful offboard engines are attractive from a parallel processing point of view, since they migrate processing and data movement ....

....factor. It is hard to blame the designers, as networking at this speed was probably not a consideration in bringing the machine to fruition. Our research plans for the immediate future (for this interface) are threefold. First, we will interconnect it to the ATM host interface designed by Davie [12] of Bellcore, and to the Sunshine switch [13] in the context of the AURORA collaboration. This will help to iron out any misinterpretations of standards or unwarranted assumptions. Second, our colleagues at IBM Research have implemented an ORBIT [6] card for the RISC System 6000 s Micro Not For ....

Bruce S. Davie, "A Host-Network Interface Architecture for ATM," in Proceedings, SIGCOMM 1991, Zurich, SWITZERLAND (September 4-6, 1991), pp. 307-315.

....using the CPU is often used to move data over the boundary. Copying means that the data must be transferred out of and into memory. The transfer of data in and out of memory is one of the main performance bottlenecks in the implementation of high speed communication for workstation class computers [7, 14, 9, 6, 15, 16]. The reason being that the bandwidth of the communication network is approaching that of memory and bus bandwidths in these systems. Reducing memory bandwidth utilization can substantially improve performance. As an example, Druschel and Peterson [10] measures the cost 1 to copy a memory page ....

....buffers. Several others have also worked on data movement, both in the context of operating systems [19, 13, 11] and network adapters [14, 15] During the last few years several high performance host network adapters have been designed. Some of them use DMA to transfer data to host memory [7, 18] and others utilize a large on board shared buffer memory [6, 2] 6 Conclusions and future work We have described a communication subsystem architecture which is designed for Integrated Layer Processing and Application Layer Framing including a concrete no copy application program interface. ....

Bruce S. Davie. A host-network interface architecture for ATM. In SIGCOMM '91 Conference Proceedings, pages 307--315, Zurich, Switzerland, September 3--6, 1991. ACM SIGCOMM Computer Communication Review, 21(4).

....logic. DEC turbochannel DEC turbochannel 32 bits x 25 MHz. 32 bits x 25 MHz. Turbochannel Option Rom Xilinx Boot Xilinx Boot ROM ROM Figure 2: Block diagram of the Yes V2 option module 6.1 Previous ATM interfaces for workstations. ATM interfaces for Unix workstations have been reported by Davie [3] and Traw [18] These are both high functionality interfaces. Traw s controller adapts ATM cells on a 155 Mbit s SONET STS 3 carrier to an IBM RS 6000 Microchannel and performs sorting of received cells in microcoded hardware. However it does not implement reassembly check functions. Davie s ....

....it should at least be possible when using a local ATM LAN. The ATM LAN may be connected to B ISDN at one or more points. The entity at the B ISDN to ATM LAN boundary can then use associative techniques if necessary 11 . An interface which can support 64000 active VCIs is deemed sufficient by [3], and we would agree. Custom and semi custom VLSI are being used to implement an ATM LAN controller. These devices connect to OEM host bus controllers, such as those available for EISA, Turbochannel, VME etc. and to inexpensive fibre optic physical layer devices, such as the AMD FOXI parts, or ....

Bruce S Davie. A host-network interface architecture for atm. In Proceedings of SIGCOMM 91 Zurich, September 1991.

....Intel 80960) and programmable logic devices. The architectural tradeoffs were discussed in a paper at COMPCON [11] a detailed description of the design, which is the product of much collaboration between Davie at Bellcore and Clark and Tennenhouse of MIT, has been recently submitted to SIGCOMM [12]. Whereas the RS6000 design described below consists entirely of dedicated hardware, the Turbochannel interface uses a combination of dedicated hardware (for functions such as cell formatting and data movement) with embedded controllers, which perform those functions that require flexibility, such ....

B. S. Davie. A host-network interface architecture for ATM. To appear in Proc. ACM SIGCOMM '91, Zurich, September 1991.

....and host interface takes a lot of time. Thus, the design of the HIF should not force DTM drivers to copy data between host 3 A B 1 4 2 Node Nr of slots Fiber A Fiber B December 2, 1993 5:27 pm 17 memory and the HIF. Similar design considerations have been made for other host interfaces, see [3][21] FIGURE 10. Host interface To avoid copying of data the HIF is based on a shared memory accessed both by the host and the HIF. Such a design has been used also by others for the same reason, see for instance [3] In the shared memory, the host writes data to be sent on the network, and reads ....

....HIF. Similar design considerations have been made for other host interfaces, see [3] 21] FIGURE 10. Host interface To avoid copying of data the HIF is based on a shared memory accessed both by the host and the HIF. Such a design has been used also by others for the same reason, see for instance [3]. In the shared memory, the host writes data to be sent on the network, and reads data received from the network. Control information to from the host is read written in a special area in the shared memory. The shared memory is divided into equally sized buffers (of typically 1 10 Kilobytes) ....

B. S Davie: "A Host-Network Interface Architecture for ATM" In Proc. ACM SIGCOMM `91, Zurich, Sep. 1991.

....it would be advantageous to increase the length of DMA transfers. In the transmit direction, the only penalty for increasing DMA length is an increase in the granularity of multiplexing. It has been argued that fine grained multiplexing is advantageous for latency and switch performance reasons [Dav91] However, when the adaptor is used in a mode where the goal is to maximize throughput to a single application, neither of these reasons is relevant. It is therefore reasonable, and straightforward, to perform DMA transactions longer than one ATM cell. Note that with transfers of 88 bytes at a ....

....3. 2) HP91] The hardware platform consists of a pair of DecStation 5000 200 workstations (25MHz MIPS R3000 CPU, 64 64 KB I D caches, 16 MB of main memory) each of which was attached to a prototype ATM network interface board, called Osiris, designed by Bellcore for the Aurora Gigabit testbed [Dav91] The Osiris boards were connected by a null modem, and they support a link speed of 622Mbps. For all results reported in this section, each data point is the average of 10 trials, where each trial consists of sending 100,000 messages, after an initial warm up period. In all cases, the 90 ....

Bruce S. Davie. A host-network interface architecture for ATM. In Proceedings of the SIGCOMM '91 Conference, pages 307--315, Zuerich, Switzerland, September 1991.

....network, our results show how to give good performance to best effort traffic while making efficient use of the resources left over by real time traffic. Fifth, our results may find application in local area ATM networks. ATM is rapidly gaining popularity in local area environments [3] 17] [22] [64] 95] This popularity is due both to the service integration advantages of cell based networks over packet based networks and to the benefits of point to point networks over broadcast networks [87] Many of the traffic multiplexing issues we have addressed in the context of wide area ....

B. S. Davie, A Host-Network Interface Architecture for ATM, Proc. of ACM SIGCOMM '91, Zurich, Switzerland, September, 1991.

....advances in workstation processor and memory subsystem performance, the next generation of high speed (Gbps) wide area networks [11] threatens to exceed the data management capabilities of the hosts. To assist these hosts, specialized host interfaces are being developed at Penn [12] Bellcore [7], Carnegie Mellon Fore Systems [4] and elsewhere. The host interface work at Penn has been centered on developing a high performance host interface for workstation hosts in the AURORA Gigabit Testbed environment [3] We have chosen to focus on workstations since we believe that they will be the ....

....logic. The host is responsible for all higher level activities. We anticipate this combination will meet our goals and provide an excellent balance between performance and flexibility. Other possibilities include a minimal hardware approach [4] or the use of powerful offboard processing engines [7]. The minimal hardware approach, characterized by the assignment of almost all tasks to the workstation host including adaptation layer processing, has two potential failings. First, RISC workstations are optimized for Not For Distribution: For Professional Review ONLY 2 data processing, ....

[Article contains additional citation context not shown here]

Bruce S. Davie, "A Host-Network Interface Architecture for ATM," in Proceedings, SIGCOMM 1991, Zurich, SWITZERLAND (September 4-6, 1991), pp. 307-315. Not For Distribution: For Professional Review ONLY! - 11 -

....on the University of Arizona s x kernel (Version 3. 2) 10] The hardware platform consists of a pair of DecStation 5000 200 workstations (25MHz MIPS R3000) each of which was attached to a prototype ATM network interface board, called Osiris, designed by Bellcore for the Aurora Gigabit testbed [6]. The Osiris boards were connected by a null modem, and support a link speed of 622Mbps. The x kernel based network subsystem consists of a protocol graph that can span multiple protection domains, including the Mach microkernel. Proxy objects are used in the x kernel to forward cross domain ....

B. S. Davie. A host-network interface architecture for ATM. In Proceedings of the SIGCOMM '91 Conference, pages 307--315, Zuerich, Switzerland, Sept. 1991.

....works. Research projects such as VMTP [24] and x kernel [25] represent examples of numerous efforts to construct frameworks for high performance transport protocol implementations. In order to further improve efficiency, new ATM host network interface designs have been proposed by Davie [26], Traw and Smith [27] and Moors and Cantoni [28] where the software bottleneck is reduced by providing hardware support for several aspects of protocol processing. Researchers concentrating on distributed computing have also proposed significant changes in operating system services that ....

B. S. Davie, "A host-network interface architecture for ATM," ACM Communication Review, pp. 307--315, 1991.

....# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # Table II: ATM oriented features Legend: HW Hardware HSW Host Software OSW Outboard Software Less protocol processing is performed by two ATM host interfaces developed at Bellcore and Penn. Bellcore s [12] ATM Host Interface implementation attaches to the TURBOChannel bus of the DECstation 5000 workstation. The interface operates on cells, and communicates protocol data units (PDUs) to and from the host. Like the CAB, this host interface relies on programmable processors, in this case, two Intel ....

Bruce S. Davie, "A Host-Network Interface Architecture for ATM," in Proceedings, SIGCOMM 1991, Zurich, SWITZERLAND (September 4-6, 1991), pp. 307-315.

....processing, host interface designs, and architectural support. Maeda et al. [6] and Brustoloni et al. [7] have proposed new protocol suites tailored specifically for high speed networks. In order to further improve efficiency, new ATM host network interface designs have been proposed by Davie [8], Traw and Smith [9] and Moors and Cantoni [10] where the software bottleneck is reduced by providing hardware support for several aspects of protocol processing. Researchers concentrating on distributed computing have also proposed significant changes in operating system services that ....

B. S. Davie, "A host-network interface architecture for ATM," ACM Communication Review, pp. 307--315, 1991.

....argue that in the case of TCP IP the actual protocol processing is of low cost and requires very few instructions on a per packet basis, and thus could be left in the host with minimal impact. Less protocol processing is performed by two ATM host interfaces built at Bellcore and Penn. Bellcore s [10] ATM Host Interface implementation attaches to the TURBOChannel bus of the DECstation 5000 workstation. The interface operates on cells, and communicates protocol data units (PDUs) to and from the host. The design relies on two Intel 80960 RISC microcontrollers to perform the protocol processing ....

Bruce S. Davie, "A Host-Network Interface Architecture for ATM," in Proceedings, SIGCOMM 1991, Zurich, SWITZERLAND (September 4-6, 1991), pp. 307-315.

....without merit, as such approaches can take significant advantage of aggressive workstation technology improvements. Our ATM host interface is one of two being designed for the AURORA Testbed environment; Davie reports on an implementation for the TURBOChannel bus of the DECstation 5000 workstation [17]. The design relies on two Intel 80960 RISC microcontrollers to perform the protocol processing and flow control for a trunk group of four STS 3c lines (622 Mbps) Such powerful off board processors are attractive in many respects, since they migrate processing and data movement tasks away from ....

....In this case, the added latency is insignificant in comparison with that added by the host software required for processing higher layers of the protocol. We felt that all per cell functions were suitable for implementation in hardware, thus avoiding the need for a processor in the host interface [17] or heavy reliance on the host processor for cell processing functions [11] 3.1. Implementation Technology Choices We have chosen to implement this architecture with relatively low cost, commercially available memories and high density programmable logic devices [3] By avoiding high clock ....

[Article contains additional citation context not shown here]

Bruce S. Davie, "A Host-Network Interface Architecture for ATM," in Proceedings, SIGCOMM 1991, Zurich, SWITZERLAND (September 4-6, 1991), pp. 307-315.

....impact on the architecture of this interface. A host interface that will provide considerable flexibility (for example, allowing experimentation with a variety of segmentation and reassembly protocols) is being implemented using embedded controllers (the Intel 80960) and programmable logic devices [15, 16]. Whereas the ATM interface to the RS 6000 (described below) consists entirely of dedicated hardware, the turbochannel interface uses a combination of dedicated hardware (for functions such as cell formatting and data movement) with embedded controllers. The controllers perform those functions ....

B. S. Davie. A host-network interface architecture for ATM. To appear in Proc. ACM SIGCOMM '91, Zurich, September 1991.

....it would be advantageous to increase the length of DMA transfers. In the transmit direction, the only penalty for increasing DMA length is an increase in the granularity of multiplexing. We argued previously that fine grained multiplexing is advantageous for latency and switch performance reasons [7]. However, when the adaptor is used in a mode where the goal is to maximize throughput to a single application, neither of these reasons is relevant. It is therefore reasonable, and straightforward, to modify the DMA controller so that it can perform DMA transactions longer than one ATM cell. Note ....

B. S. Davie. A host-network interface architecture for ATM. In Proc. ACMSIGCOMM '91, Zurich, September 1991.

....impact on the architecture of this interface. A host interface that will provide considerable flexibility (for example, allowing experimentation with a variety of segmentation and reassembly protocols) is being implemented using embedded controllers (the Intel 80960) and programmable logic devices [8]. Whereas the ATM interface to the RS 6000 (described below) consists entirely of dedicated hardware, the turbochannel interface uses a combination of dedicated hardware (for functions such as cell formatting and data movement) with embedded controllers. The controllers perform those functions ....

B. S. Davie. A host-network interface architecture for ATM. In Proc. ACM SIGCOMM '91, Zurich, Sept. 1991.

No context found.

B. S. Davie, \A Host-network Interface Architecture for ATM," ACM Proc. Sigcomm, pp. 307-16, September 1991.

No context found.

B. S. Davie, "A host-network interface architecture for ATM," Proceedings of ACM SIGCOMM '91,ACM, Zurich, Switzerland, 1991.

No context found.

B. Davie, "A Host-Network Interface Architecture for ATM," Proceedings of the Symposium on Communications Architectures and Protocols, ACM SIGCOMM 1991, ACM Computer Communication Review, vol. 21, no. 4 (September 1991).

No context found.

B.S. Davie, "A Host-Network Interface Architecture for ATM", Bell Communications Research, Morristown, NJ.

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