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B. A. Fields, S. Rubin, et al. Focusing processor policies via critical-path prediction. In International Symposium on Computer Architecture (ISCA), 2001.

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Microarchitectural Trade-offs in the Design of a.. - Balasubramonian..   (Correct)

....is given to data dependences, issue queue load, and register pressure. Each simulated clustered organization was optimized by trying various threshold values and picking the set that performed best. The steering heuristic also incorporates a criticality predictor similar to those proposed recently [14, 28]. A simple table indexed by program counter predicts which of the two operands of an instruction is likely to be produced later and the corresponding data dependence is given a higher weight in the equation. Once loads and stores are ready, they are inserted into a centralized load store queue ....

B. Fields, S. Rubin, and R. Bodik. Focusing Processor Policies via Critical-Path Prediction. In Proceedings of ISCA-28, July 2001.


Joint Local and Global Hardware Adaptations for Energy - Ruchira Sasanka Christopher (2002)   (7 citations)  (Correct)

....of the possible overlap for the consumer because the producers of the other operands of the consumer may not be able to provide that much overlap with a larger instruction window. The idea of passing tags was inspired by the token passing along last arriving edges of Fields et al. [10] The value of IWtag gives the additional overlap that an instruction could get with a larger window. If a tagged instruction stalls the processor for S cycles, then we estimate min(IW tag; S) as the number of stall cycles that could be avoided by the additional overlap. We accumulate the ....

B. Fields, S. Rubin, and R. Bodk. Focusing Processor Policies via Critical-Path Prediction. In Proc. of the 28th Annual Intl. Symp. on Comp. Architecture, 2001.


Performance and Energy Impact of Instruction-Level Value.. - Bhargava, John (2003)   (Correct)

....[22] Their architecture allows only one value prediction per cycle (one read port) Critical Path Prediction is used to determine which instructions will use this resource. Fields et al. also propose a mechanism to isolate critical instructions, but they apply it only to value prediction update [9]. Rychlik et al. discuss the usefulness of value predictions [19] For SPEC CPU95, they observe that 31 (integer programs) and 62 (floating point programs) of predicted values are never read before they are overwritten by the final result. The authors introduce a mechanism which only updates ....

B. Fields, S. Rubin, and R. Bodik. Focusing processor policies via critical-path prediction. In 28th International Symposium on Computer Architecture, pages 74--85, Jul 2001.


TCP: Tag Correlating Prefetchers - Hu, Martonosi, Kaxiras (2003)   (3 citations)  (Correct)

....to a DBCP with a 2 MB correlation history table. Dead block correlating prefetcher (DBCP) 12] is a correlation based prefetcher that correlates the liveness of a cache line and the next tag with PCs of memory instructions, in addition to addresses. Note that in [12] a critical miss predictor [20, 6] is proposed to filter the correlation entries. In our experiment, this filter is not incorporated in either DBCP or TCP. In general, the two TCP prefetchers both out perform DBCP. On average, DBCP achieves about 7 performance improvement, while TCP 8K and TCP 8M can achieve about 0 20 40 60 ....

....targets, which we hope to investigate. Since not all cache misses affect performance equally, a critical miss filter may also be useful in future investigations. Many researchers have tried to identify those misses that are critical for program performance and devise optimizations targeting them [20, 6]. Prefetchers can benefit from such a critical miss predictor in many ways. For example, only prefetches for critical misses will be issued, so that the prefetch induced extra traffic can be reduced. In [12] only the correlation patterns of critical misses are stored, so that the space efficiency ....

B. Fields, S. Rubin, and R. Bodik. Focusing Processor Policies via Critical-Path Prediction. In Proc. 28th Annual Intl. Symp. on Computer Architecture, July 2001.


Detecting Global Stride Locality in Value Streams - Zhou, Flanagan, Conte (2003)   (3 citations)  (Correct)

....(e.g. the local stride predictor) The correct values produced after execution are used to update the value sequence. In this way, the gDiff predictor maximizes exploiting global value locality and (This suggests that a further enhancement to gDiff would combine it with a critical path predictor [5, 29], but such an extension is beyond the scope of this paper. enables an efficient integration of a different type of value locality. The experiments show that the gDiff predictor achieves an impressive 91 prediction accuracy with 64 coverage. We then demonstrate the usage of gDiff prediction ....

B. Fields, S. Rubin, and R. Bodik, "Focusing processor policies via critical-path prediction", in International Symposium on Computer Architecture (ISCA-28), 2001.


Half-Price Architecture - Kim, Lipasti (2003)   (1 citation)  (Correct)

....require two read port accesses from the register file as the bypass opportunity decreases. We did not study sequential register access on a clustered microarchitecture and leave it as future work because performance is highly dependent on the cluster steering policy. However, many researchers [12][21][22] have studied steering policies for reducing inter cluster communication and hiding its delay on such microarchitectures; the same policies can be used in favor of sequential register access to minimize performance impact. 4.2. Characterization of register read port accesses Bypass logic is ....

B. Fields, S. Rubin and R. Bodik, Focusingprocessorpolicies via critical-path prediction, in Proc. of 28th International Symposium on Microarchitecture, 2001.


Cluster Assignment Strategies for a Clustered Trace Cache.. - Bhargava, John (2003)   (Correct)

....FDRT FDRT ROB Stall Figure 11: Performance E#ect of Incorporating ROB Stall Information 25 Overall, this new modification did not provide the desired result. Further work needs to be done to recognize, critical chains of instructions instead of just the instructions at the end of the chain [19, 4]. This way all the instructions int the dependency chain can be assigned to the same cluster instead. Chaining Intra Trace Dependencies In Figure 12, FDRT Chain Intra Trace Deps represents allowing instructions that have an intra trace dependency with their producer to be part of the pinned ....

B. Fields, S. Rubin, and R. Bodik. Focusing processor policies via critical-path prediction. In 28th International Symposium on Computer Architecture, pages 74--85, Jul 2001.


Dynamic Data Dependence Tracking and its Application to.. - Chen, Dropsho, Albonesi   (Correct)

....(e.g. branch predictors, out of order issue queues) that are purely used for performance purposes. We enumerate some of the many applications for such on line data dependence information. These include dynamic scheduling, selective value prediction [6] criticality measures and their application [11, 29, 30], and decoupled architectures [3, 33] to name a few. We then investigate in depth how dynamic data dependence information can be exploited to provide another dimension for branch prediction. Our approach, called ARVI, bases its prediction on partial register values along the data dependence chain ....

....a more accurate parallelism estimate to guide these and other parallelism based optimizations. Improving the accuracy of criticality measures: Load criticality was originally investigated by Srinivasan and Lebeck [29, 30] in order to improve load performance. Other researchers, including Bodik [11], have proposed techniques for identifying critical instructions. Cycle by cycle dependence chain information can potentially improve the accuracy of critical instruction detection. For instance, Bodik s random sampling approach may unintentionally miss critical sequences. Data dependence ....

B. Fields, S. Rubin, and R. Bodik. Focusing Processor Policies via Critical-Path Prediction. 28th Annual International Symposium on Computer Architecture, pages 74--85, June 2001.


Energy-Efficient Processor Design Using Multiple.. - Semeraro.. (2002)   (13 citations)  (Correct)

....manages system power. They use this monitoring system in order to demonstrate how to set the threshold idle time used to place a disk in low power mode. Our work differs in that we attempt to slow down only those parts of the processor that are not on an application s critical path. Fields et al. [12] use a dependence graph similar to ours, but constructed on the fly, to identify the critical path of an application. Their goal is to improve instruction steering in clustered architectures and to improve value prediction by selectively applying it to critical instructions only. We use our graph ....

B. Fields, S. Rubin, and R. Bodik. Focusing Processor Policies via Critical-Path Prediction. In Proceedings of the 28th International Symposium on Computer Architecture, July 2001.


Using Interaction Costs for Microarchitectural.. - Fields, Bodik, Hill..   Self-citation (Fields Bodk)   (Correct)

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B. Fields, S. Rubin, and R. Bodk. Focusing processor policies via critical-path prediction. In 28 International Symposium on Computer Architecture, Jun 2001.


Slack: Maximizing Performance Under Technological Constraints - Fields, Bodik, Hill (2002)   (11 citations)  Self-citation (Fields Bodk)   (Correct)

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B. Fields, S. Rubin, and R. Bodk. Focusing processor policies via critical-path prediction. In Proceedings of the 28th Annual International Symposium on Computer Architecture, Jun-- Jul 2001.


Dataflow: A Complement to Superscalar - Budiu, Artigas, Goldstein (2005)   (Correct)

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B. A. Fields, S. Rubin, et al. Focusing processor policies via critical-path prediction. In International Symposium on Computer Architecture (ISCA), 2001.


Hardware Support for Thread-Level Speculation - Steffan (2003)   (Correct)

No context found.

Brian A. Fields, Shai Rubin, and Rastislav Bodik. Focusing processor policies via critical-path prediction. In ISCA 2001.


A Large, Fast Instruction Window for Tolerating Cache Misses - Alvin Lebeck Jinson   (Correct)

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B. A. Fields, S. Rubin, and R. Bodik. Focusing Processor Policies via Critical-Path Prediction. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 74--85, July 2001.


A Quantitative Framework for Automated . . . - Roth, al. (2002)   (Correct)

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B. Fields, S. Rubin, and R. Bodik. "Focusing Processor Policies via Critical Path Prediction." In Proc. 27th Annual International Symposium on Computer Architecture, pages 74--85, Jul. 2001.


Instruction History Management for High-Performance Microprocessors - Bhargava (2003)   (Correct)

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B. Fields, S. Rubin, and R. Bodik. Focusing processor policies via critical-path prediction. In 28th International Symposium on Computer Architecture, pages 74--85, July 2001.


Spatial Computation - Budiu (2003)   (Correct)

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Brian A Fields, Shai Rubin, and Rastislav Bod k. Focusing processor policies via criticalpath prediction. In International Symposium on Computer Architecture (ISCA), 2001.


Performance Implications Of Future-Generation Memory Systems.. - Fertig (2003)   (1 citation)  (Correct)

No context found.

B. A. Fields, S. Rubin, and R. Bodik, \Focusing processor policies via critical-path prediction," in Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001, pp. 74-85, http://citeseer.nj.nec.com/fields01focusing.html.


Hardware Support for Thread-Level Speculation - Steffan (2003)   (Correct)

No context found.

Brian A. Fields, Shai Rubin, and Rastislav Bodik. Focusing processor policies via critical-path prediction. In ISCA 2001.


Power Efficient Data Cache Designs - Jaume Abella Antonio   (Correct)

No context found.

B. Fields, S. Rubin, R. Bodk, "Focusing Processor Policies via Critical-Path Prediction" in ISCA'01, Gteborg, Sweden, June 2001.


TCP: Tag Correlating Prefetchers - Hu, Martonosi, Kaxiras (2003)   (3 citations)  (Correct)

No context found.

B. Fields, S. Rubin, and R. Bodik. Focusing Processor Policies via Critical-Path Prediction. In Proc. 28th Annual Intl. Symp. on Computer Architecture, July 2001.


Mesocode: Optimizations for Improving Fetch.. - Eng, Wang, Wang..   (Correct)

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B. Fields, S. Rubin, and R. Bodik. Focusing Processor Policies via Critical-Path Prediction. In Proc. 28 Int'l Symp. on Computer Architecture, pp. 74-85, July 2001.


A Large, Fast Instruction Window for Tolerating Cache.. - Li, Koppanalil.. (2002)   (Correct)

No context found.

B. A. Fields, S. Rubin, and R. Bodik. Focusing Processor Policies via Critical-Path Prediction. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 74--85, July 2001.


Permission to Make Digital Or Hard Copies of All Or Part.. - Personal Or Classroom   (Correct)

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Brian Fields, Shai Rubin, and Rastislav Bodik. Focusing Processor Policies via Critical-Path Prediction. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 74--85, July 2001.


A Large, Fast Instruction Window for Tolerating Cache.. - Lebeck, Koppanalil..   (Correct)

No context found.

B. A. Fields, S. Rubin, and R. Bodik. Focusing Processor Policies via Critical-Path Prediction. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 74--85, July 2001.

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