V. Moshnyaga, K. Tamaru, "Effect of Technology Scaling on Area-Delay Characteristics of RTL Designs: A Case Study", In proceedings of ED&TC'97, pp. 75-79, 1997. Home/Search Document Details and Download
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Interconnect Cost Control during High-Level Synthesis - Jego, Casseau, Martin (2000) (Correct)
.... integration features (CMOS technology) Such scaling implies that the circuit performance will be increasingly determined by the interconnection performance : the wiring delay percentage relative to the cycle time actually becomes more important than the operator propagation time percentage [4,5]. For instance, interconnection can contribute up to 50 percent of the total delay in 0.35 m and is expected to contribute up to 70 percent in 0.25 m [5] Whereas this interconnection cost was not of major importance with technologies greater than 0.5 m, interconnection design will play a crucial ....
V. Moshnyaga, K. Tamaru, "Effect of Technology Scaling on Area-Delay Characteristics of RTL Designs: A Case Study", In proceedings of ED&TC'97, pp. 75-79, 1997.
Architectural Synthesis with Interconnection Cost Control - Jego, Casseau, Martin (1999) (Correct)
....integration features in CMOS technology. Such scaling implies that the circuit performance will be increasingly determined by the interconnection performance : the wiring delay percentage relative to the cycle time actually becomes more important than the operator propagation time percentage [6,7]. For instance, interconnection contributes 50 percent of total delay in 0.35 m and is expected to contribute up to 70 percent in 0.25 m. Whereas this interconnection cost was not of great importance with technologies above 0.7 m, interconnection design will play the most critical role in ....
V. Moshnyaga, K. Tamaru, "Effect of Technology Scaling on Area-Delay Characteristics of RTL Designs: A Case Study", In proceedings of ED&TC'97, pp. 75-79, 1997.
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